mirror of https://github.com/YosysHQ/icestorm.git
41 lines
652 B
Verilog
41 lines
652 B
Verilog
module testbench;
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reg clk;
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always #5 clk = (clk === 1'b0);
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wire ok;
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top uut (
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.clk(clk),
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.LED5(ok)
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);
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reg [4095:0] vcdfile;
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initial begin
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if ($value$plusargs("vcd=%s", vcdfile)) begin
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$dumpfile(vcdfile);
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$dumpvars(0, testbench);
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end
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end
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initial begin
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@(posedge ok);
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@(negedge ok);
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$display("ERROR: detected falling edge on OK pin!");
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$stop;
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end
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initial begin
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repeat (3000) @(posedge clk);
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if (!ok) begin
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$display("ERROR: OK pin not asserted after 3000 cycles!");
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$stop;
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end
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repeat (10000) @(posedge clk);
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$display("SUCCESS: OK pin still asserted after 10000 cycles.");
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$finish;
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end
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endmodule
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