mirror of https://github.com/YosysHQ/icestorm.git
80 lines
1.2 KiB
Verilog
80 lines
1.2 KiB
Verilog
module testbench;
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localparam integer PERIOD = 12000000 / 9600;
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// reg clk = 0;
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// initial #10 forever #5 clk = ~clk;
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reg clk;
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always #5 clk = (clk === 1'b0);
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reg RX = 1;
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wire TX;
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wire LED1;
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wire LED2;
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wire LED3;
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wire LED4;
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wire LED5;
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top uut (
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.clk (clk ),
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.RX (RX ),
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.TX (TX ),
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.LED1(LED1),
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.LED2(LED2),
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.LED3(LED3),
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.LED4(LED4),
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.LED5(LED5)
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);
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task send_byte;
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input [7:0] c;
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integer i;
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begin
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RX <= 0;
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repeat (PERIOD) @(posedge clk);
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for (i = 0; i < 8; i = i+1) begin
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RX <= c[i];
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repeat (PERIOD) @(posedge clk);
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end
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RX <= 1;
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repeat (PERIOD) @(posedge clk);
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end
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endtask
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reg [4095:0] vcdfile;
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initial begin
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if ($value$plusargs("vcd=%s", vcdfile)) begin
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$dumpfile(vcdfile);
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$dumpvars(0, testbench);
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end
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repeat (10 * PERIOD) @(posedge clk);
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// turn all LEDs off
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send_byte("1");
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send_byte("3");
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send_byte("5");
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// turn all LEDs on
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send_byte("1");
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send_byte("2");
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send_byte("3");
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send_byte("4");
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send_byte("5");
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// turn all LEDs off
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send_byte("1");
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send_byte("2");
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send_byte("3");
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send_byte("4");
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send_byte("5");
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repeat (10 * PERIOD) @(posedge clk);
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$finish;
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end
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endmodule
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