mirror of https://github.com/YosysHQ/icestorm.git
65 lines
1.4 KiB
Verilog
65 lines
1.4 KiB
Verilog
`define CONN_INTERNAL_BITS
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`define PINTYPE 6'b010000
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// `define IOSTANDARD "SB_LVCMOS"
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`define IOSTANDARD "SB_LVDS_INPUT"
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// The following IO standards are just aliases for SB_LVCMOS
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// `define IOSTANDARD "SB_LVCMOS25_16"
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// `define IOSTANDARD "SB_LVCMOS25_12"
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// `define IOSTANDARD "SB_LVCMOS25_8"
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// `define IOSTANDARD "SB_LVCMOS25_4"
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// `define IOSTANDARD "SB_LVCMOS18_10"
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// `define IOSTANDARD "SB_LVCMOS18_8"
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// `define IOSTANDARD "SB_LVCMOS18_4"
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// `define IOSTANDARD "SB_LVCMOS18_2"
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// `define IOSTANDARD "SB_LVCMOS15_4"
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// `define IOSTANDARD "SB_LVCMOS15_2"
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// `define IOSTANDARD "SB_MDDR10"
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// `define IOSTANDARD "SB_MDDR8"
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// `define IOSTANDARD "SB_MDDR4"
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// `define IOSTANDARD "SB_MDDR2"
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`ifdef CONN_INTERNAL_BITS
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module top (
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inout pin,
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input latch_in,
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input clk_in,
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input clk_out,
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input oen,
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input dout_0,
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input dout_1,
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output din_0,
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output din_1
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);
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`else
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module top(pin);
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inout pin;
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wire latch_in = 0;
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wire clk_in = 0;
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wire clk_out = 0;
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wire oen = 0;
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wire dout_0 = 0;
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wire dout_1 = 0;
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wire din_0;
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wire din_1;
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`endif
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SB_IO #(
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.PIN_TYPE(`PINTYPE),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0),
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.IO_STANDARD(`IOSTANDARD)
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) IO_PIN_I (
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.PACKAGE_PIN(pin),
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.LATCH_INPUT_VALUE(latch_in),
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.CLOCK_ENABLE(clk_en),
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.INPUT_CLK(clk_in),
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.OUTPUT_CLK(clk_out),
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.OUTPUT_ENABLE(oen),
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.D_OUT_0(dout_0),
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.D_OUT_1(dout_1),
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.D_IN_0(din_0),
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.D_IN_1(din_1)
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);
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endmodule
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