mirror of https://github.com/YosysHQ/icestorm.git
1139 lines
43 KiB
Python
1139 lines
43 KiB
Python
#!/usr/bin/python
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#
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# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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from __future__ import division
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from __future__ import print_function
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import iceboxdb
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import re, sys
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class iceconfig:
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def __init__(self):
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self.clear()
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def clear(self):
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self.max_x = 0
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self.max_y = 0
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self.device = ""
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self.logic_tiles = dict()
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self.io_tiles = dict()
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self.ramb_tiles = dict()
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self.ramt_tiles = dict()
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self.ram_data = dict()
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self.extra_bits = set()
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def setup_empty_1k(self):
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self.clear()
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self.device = "1k"
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self.max_x = 13
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self.max_y = 17
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for x in range(1, self.max_x):
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for y in range(1, self.max_y):
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if x in (3, 10):
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if y % 2 == 1:
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self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)]
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else:
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self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)]
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else:
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self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)]
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for x in range(1, self.max_x):
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self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)]
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self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)]
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for y in range(1, self.max_y):
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self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)]
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self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)]
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def lookup_extra_bit(self, bit):
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assert self.device in extra_bits_db
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if bit in extra_bits_db[self.device]:
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return extra_bits_db[self.device][bit]
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return ("UNKNOWN_FUNCTION",)
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def tile(self, x, y):
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if (x, y) in self.io_tiles: return self.io_tiles[(x, y)]
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if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)]
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if (x, y) in self.ramb_tiles: return self.ramb_tiles[(x, y)]
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if (x, y) in self.ramt_tiles: return self.ramt_tiles[(x, y)]
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return None
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def pinloc_db(self):
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assert self.device == "1k"
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return pinloc_db
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def gbufin_db(self):
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return gbufin_db[self.device]
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def iolatch_db(self):
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return iolatch_db[self.device]
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def padin_pio_db(self):
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return padin_pio_db[self.device]
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def extra_bits_db(self):
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return extra_bits_db[self.device]
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def ieren_db(self):
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return ieren_db[self.device]
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def colbuf_db(self):
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assert self.device == "1k"
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entries = list()
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for x in range(self.max_x+1):
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for y in range(self.max_y+1):
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src_y = None
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if 0 <= y <= 4: src_y = 4
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if 5 <= y <= 8: src_y = 5
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if 9 <= y <= 12: src_y = 12
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if 13 <= y <= 17: src_y = 13
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if x in [3, 10] and src_y == 4: src_y = 3
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if x in [3, 10] and src_y == 12: src_y = 11
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entries.append((x, src_y, x, y))
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return entries
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def tile_db(self, x, y):
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if x == 0: return iotile_l_db
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if y == 0: return iotile_b_db
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if x == self.max_x: return iotile_r_db
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if y == self.max_y: return iotile_t_db
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if (x, y) in self.ramb_tiles: return rambtile_db
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if (x, y) in self.ramt_tiles: return ramttile_db
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if (x, y) in self.logic_tiles: return logictile_db
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assert False
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def tile_type(self, x, y):
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if x == 0: return "IO"
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if y == 0: return "IO"
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if x == self.max_x: return "IO"
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if y == self.max_y: return "IO"
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if (x, y) in self.ramb_tiles: return "RAMB"
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if (x, y) in self.ramt_tiles: return "RAMT"
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if (x, y) in self.logic_tiles: return "LOGIC"
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assert False
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def tile_pos(self, x, y):
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if x == 0 and 0 < y < self.max_y: return "l"
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if y == 0 and 0 < x < self.max_x: return "b"
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if x == self.max_x and 0 < y < self.max_y: return "r"
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if y == self.max_y and 0 < x < self.max_x: return "t"
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if 0 < x < self.max_x and 0 < y < self.max_y: return "x"
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return None
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def tile_has_entry(self, x, y, entry):
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if entry[1] in ("routing", "buffer"):
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return self.tile_has_net(x, y, entry[2]) and self.tile_has_net(x, y, entry[3])
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return True
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def tile_has_net(self, x, y, netname):
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if netname.startswith("logic_op_"):
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if netname.startswith("logic_op_bot_"):
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if y == self.max_y and 0 < x < self.max_x: return True
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if netname.startswith("logic_op_bnl_"):
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if x == self.max_x and 1 < y < self.max_y: return True
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if y == self.max_y and 1 < x < self.max_x: return True
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if netname.startswith("logic_op_bnr_"):
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if x == 0 and 1 < y < self.max_y: return True
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if y == self.max_y and 0 < x < self.max_x-1: return True
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if netname.startswith("logic_op_top_"):
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if y == 0 and 0 < x < self.max_x: return True
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if netname.startswith("logic_op_tnl_"):
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if x == self.max_x and 0 < y < self.max_y-1: return True
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if y == 0 and 1 < x < self.max_x: return True
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if netname.startswith("logic_op_tnr_"):
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if x == 0 and 0 < y < self.max_y-1: return True
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if y == 0 and 0 < x < self.max_x-1: return True
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if netname.startswith("logic_op_lft_"):
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if x == self.max_x: return True
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if netname.startswith("logic_op_rgt_"):
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if x == 0: return True
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return False
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if not 0 <= x <= self.max_x: return False
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if not 0 <= y <= self.max_y: return False
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return pos_has_net(self.tile_pos(x, y), netname)
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def tile_follow_net(self, x, y, direction, netname):
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if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname)
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if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname)
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if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname)
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if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname)
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return pos_follow_net(self.tile_pos(x, y), direction, netname)
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def follow_funcnet(self, x, y, func):
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neighbours = set()
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def do_direction(name, nx, ny):
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if 0 < nx < self.max_x and 0 < ny < self.max_y:
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neighbours.add((nx, ny, "neigh_op_%s_%d" % (name, func)))
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if nx in (0, self.max_x) and 0 < ny < self.max_y and nx != x:
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neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func)))
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if ny in (0, self.max_y) and 0 < nx < self.max_x and ny != y:
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neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func)))
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do_direction("bot", x, y+1)
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do_direction("bnl", x+1, y+1)
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do_direction("bnr", x-1, y+1)
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do_direction("top", x, y-1)
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do_direction("tnl", x+1, y-1)
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do_direction("tnr", x-1, y-1)
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do_direction("lft", x+1, y )
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do_direction("rgt", x-1, y )
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return neighbours
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def lookup_funcnet(self, nx, ny, x, y, func):
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npos = self.tile_pos(nx, ny)
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pos = self.tile_pos(x, y)
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if npos is not None and pos is not None:
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if npos == "x":
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if (nx, ny) in self.logic_tiles:
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return (nx, ny, "lutff_%d/out" % func)
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if (nx, ny) in self.ramb_tiles:
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return (nx, ny, "ram/RDATA_%d" % func)
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if (nx, ny) in self.ramt_tiles:
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return (nx, ny, "ram/RDATA_%d" % (8+func))
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elif pos == "x" and npos in ("l", "r", "t", "b"):
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if func in (0, 4): return (nx, ny, "io_0/D_IN_0")
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if func in (1, 5): return (nx, ny, "io_0/D_IN_1")
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if func in (2, 6): return (nx, ny, "io_1/D_IN_0")
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if func in (3, 7): return (nx, ny, "io_1/D_IN_1")
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return None
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def rlookup_funcnet(self, x, y, netname):
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funcnets = set()
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if netname == "io_0/D_IN_0":
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for net in self.follow_funcnet(x, y, 0) | self.follow_funcnet(x, y, 4):
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if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net)
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if netname == "io_0/D_IN_1":
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for net in self.follow_funcnet(x, y, 1) | self.follow_funcnet(x, y, 5):
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if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net)
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if netname == "io_1/D_IN_0":
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for net in self.follow_funcnet(x, y, 2) | self.follow_funcnet(x, y, 6):
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if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net)
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if netname == "io_1/D_IN_1":
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for net in self.follow_funcnet(x, y, 3) | self.follow_funcnet(x, y, 7):
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if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net)
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match = re.match(r"lutff_(\d+)/out", netname)
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if match:
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funcnets |= self.follow_funcnet(x, y, int(match.group(1)))
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match = re.match(r"ram/RDATA_(\d+)", netname)
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if match:
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funcnets |= self.follow_funcnet(x, y, int(match.group(1)) % 8)
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return funcnets
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def follow_net(self, netspec):
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x, y, netname = netspec
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neighbours = self.rlookup_funcnet(x, y, netname)
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if netname == "carry_in" and y > 1:
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neighbours.add((x, y-1, "lutff_7/cout"))
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if netname == "lutff_7/cout" and y+1 < self.max_y:
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neighbours.add((x, y+1, "carry_in"))
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if netname.startswith("glb_netwk_"):
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for nx in range(self.max_x+1):
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for ny in range(self.max_y+1):
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if self.tile_pos(nx, ny) is not None:
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neighbours.add((nx, ny, netname))
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match = re.match(r"sp4_r_v_b_(\d+)", netname)
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if match and 0 < x < self.max_x-1:
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neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1))))
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match = re.match(r"sp4_v_[bt]_(\d+)", netname)
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if match and 1 < x < self.max_x:
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n = sp4v_normalize(netname, "b")
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if n is not None:
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n = n.replace("sp4_", "sp4_r_")
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neighbours.add((x-1, y, n))
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match = re.match(r"(logic|neigh)_op_(...)_(\d+)", netname)
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if match:
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if match.group(2) == "bot": nx, ny = (x, y-1)
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if match.group(2) == "bnl": nx, ny = (x-1, y-1)
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if match.group(2) == "bnr": nx, ny = (x+1, y-1)
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if match.group(2) == "top": nx, ny = (x, y+1)
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if match.group(2) == "tnl": nx, ny = (x-1, y+1)
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if match.group(2) == "tnr": nx, ny = (x+1, y+1)
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if match.group(2) == "lft": nx, ny = (x-1, y )
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if match.group(2) == "rgt": nx, ny = (x+1, y )
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n = self.lookup_funcnet(nx, ny, x, y, int(match.group(3)))
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if n is not None:
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neighbours.add(n)
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for direction in ["l", "r", "t", "b"]:
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n = self.tile_follow_net(x, y, direction, netname)
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if n is not None:
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if direction == "l": s = (x-1, y, n)
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if direction == "r": s = (x+1, y, n)
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if direction == "t": s = (x, y+1, n)
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if direction == "b": s = (x, y-1, n)
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if s[0] in (0, self.max_x) and s[1] in (0, self.max_y):
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if re.match("span4_(vert|horz)_[lrtb]_\d+$", n):
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vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_")
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horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_")
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if s[0] == 0 and s[1] == 0:
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if direction == "l": s = (0, 1, vert_net)
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if direction == "b": s = (1, 0, horz_net)
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if s[0] == self.max_x and s[1] == self.max_y:
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if direction == "r": s = (self.max_x, self.max_y-1, vert_net)
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if direction == "t": s = (self.max_x-1, self.max_y, horz_net)
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vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_")
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horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_")
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if s[0] == 0 and s[1] == self.max_y:
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if direction == "l": s = (0, self.max_y-1, vert_net)
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if direction == "t": s = (1, self.max_y, horz_net)
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if s[0] == self.max_x and s[1] == 0:
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if direction == "r": s = (self.max_x, 1, vert_net)
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if direction == "b": s = (self.max_x-1, 0, horz_net)
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if self.tile_has_net(s[0], s[1], s[2]):
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neighbours.add((s[0], s[1], s[2]))
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return neighbours
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def group_segments(self, all_from_tiles=set(), extra_connections=list(), extra_segments=list(), connect_gb=True):
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seed_segments = set()
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seen_segments = set()
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connected_segments = dict()
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grouped_segments = set()
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for seg in extra_segments:
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seed_segments.add(seg)
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for conn in extra_connections:
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s1, s2 = conn
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connected_segments.setdefault(s1, set()).add(s2)
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connected_segments.setdefault(s2, set()).add(s1)
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seed_segments.add(s1)
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seed_segments.add(s2)
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for idx, tile in self.io_tiles.items():
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tc = tileconfig(tile)
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pintypes = [ list("000000"), list("000000") ]
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for entry in self.tile_db(idx[0], idx[1]):
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if entry[1].startswith("IOB_") and entry[2].startswith("PINTYPE_") and tc.match(entry[0]):
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pintypes[int(entry[1][-1])][int(entry[2][-1])] = "1"
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if "".join(pintypes[0][2:6]) != "0000":
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seed_segments.add((idx[0], idx[1], "io_0/D_OUT_0"))
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if "".join(pintypes[1][2:6]) != "0000":
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seed_segments.add((idx[0], idx[1], "io_1/D_OUT_0"))
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def add_seed_segments(idx, tile, db):
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tc = tileconfig(tile)
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for entry in db:
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if entry[1] in ("routing", "buffer"):
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config_match = tc.match(entry[0])
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if idx in all_from_tiles or config_match:
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if not self.tile_has_net(idx[0], idx[1], entry[2]): continue
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if not self.tile_has_net(idx[0], idx[1], entry[3]): continue
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s1 = (idx[0], idx[1], entry[2])
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s2 = (idx[0], idx[1], entry[3])
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if config_match:
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connected_segments.setdefault(s1, set()).add(s2)
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connected_segments.setdefault(s2, set()).add(s1)
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seed_segments.add(s1)
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seed_segments.add(s2)
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for idx, tile in self.io_tiles.items():
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add_seed_segments(idx, tile, self.tile_db(idx[0], idx[1]))
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for idx, tile in self.logic_tiles.items():
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if idx in all_from_tiles:
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seed_segments.add((idx[0], idx[1], "lutff_7/cout"))
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add_seed_segments(idx, tile, logictile_db)
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for idx, tile in self.ramb_tiles.items():
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add_seed_segments(idx, tile, rambtile_db)
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for idx, tile in self.ramt_tiles.items():
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add_seed_segments(idx, tile, ramttile_db)
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for padin, pio in enumerate(self.padin_pio_db()):
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s1 = (pio[0], pio[1], "wire_gbuf/padin_%d" % pio[2])
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s2 = (pio[0], pio[1], "glb_netwk_%d" % padin)
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if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles:
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connected_segments.setdefault(s1, set()).add(s2)
|
|
connected_segments.setdefault(s2, set()).add(s1)
|
|
seed_segments.add(s1)
|
|
seed_segments.add(s2)
|
|
|
|
for entry in self.iolatch_db():
|
|
if entry[0] == 0 or entry[0] == self.max_x:
|
|
iocells = [(entry[0], i) for i in range(1, self.max_y)]
|
|
if entry[1] == 0 or entry[1] == self.max_y:
|
|
iocells = [(i, entry[1]) for i in range(1, self.max_x)]
|
|
for cell in iocells:
|
|
s1 = (entry[0], entry[1], "wire_gbuf/in")
|
|
s2 = (cell[0], cell[1], "io_global/latch")
|
|
if s1 in seed_segments or s2 in seed_segments or \
|
|
(entry[0], entry[1]) in all_from_tiles or (cell[0], cell[1]) in all_from_tiles:
|
|
connected_segments.setdefault(s1, set()).add(s2)
|
|
connected_segments.setdefault(s2, set()).add(s1)
|
|
seed_segments.add(s1)
|
|
seed_segments.add(s2)
|
|
|
|
if connect_gb:
|
|
for entry in self.gbufin_db():
|
|
s1 = (entry[0], entry[1], "wire_gbuf/in")
|
|
s2 = (entry[0], entry[1], "glb_netwk_%d" % entry[2])
|
|
if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles:
|
|
connected_segments.setdefault(s1, set()).add(s2)
|
|
connected_segments.setdefault(s2, set()).add(s1)
|
|
seed_segments.add(s1)
|
|
seed_segments.add(s2)
|
|
|
|
while seed_segments:
|
|
queue = set()
|
|
segments = set()
|
|
queue.add(seed_segments.pop())
|
|
while queue:
|
|
for s in self.expand_net(queue.pop()):
|
|
if s not in segments:
|
|
segments.add(s)
|
|
assert s not in seen_segments
|
|
seen_segments.add(s)
|
|
seed_segments.discard(s)
|
|
if s in connected_segments:
|
|
for cs in connected_segments[s]:
|
|
if not cs in segments:
|
|
queue.add(cs)
|
|
for s in segments:
|
|
assert s not in seed_segments
|
|
grouped_segments.add(tuple(sorted(segments)))
|
|
|
|
return grouped_segments
|
|
|
|
def expand_net(self, netspec):
|
|
queue = set()
|
|
segments = set()
|
|
queue.add(netspec)
|
|
while queue:
|
|
n = queue.pop()
|
|
segments.add(n)
|
|
for k in self.follow_net(n):
|
|
if k not in segments:
|
|
queue.add(k)
|
|
return segments
|
|
|
|
def read_file(self, filename, logprefix=""):
|
|
self.clear()
|
|
current_data = None
|
|
expected_data_lines = 0
|
|
with open(filename, "r") as f:
|
|
for linenum, linetext in enumerate(f):
|
|
# print("DEBUG: input line %d: %s" % (linenum, linetext.strip()))
|
|
line = linetext.strip().split()
|
|
if len(line) == 0:
|
|
assert expected_data_lines == 0
|
|
continue
|
|
if line[0][0] != ".":
|
|
if expected_data_lines == -1:
|
|
continue
|
|
if line[0][0] not in "0123456789abcdef":
|
|
print("%sWarning: ignoring data block in line %d: %s" % (logprefix, linenum, linetext.strip()))
|
|
expected_data_lines = 0
|
|
continue
|
|
assert expected_data_lines != 0
|
|
current_data.append(line[0])
|
|
expected_data_lines -= 1
|
|
continue
|
|
assert expected_data_lines <= 0
|
|
if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data"):
|
|
current_data = list()
|
|
expected_data_lines = 16
|
|
self.max_x = max(self.max_x, int(line[1]))
|
|
self.max_y = max(self.max_y, int(line[2]))
|
|
if line[0] == ".io_tile":
|
|
self.io_tiles[(int(line[1]), int(line[2]))] = current_data
|
|
continue
|
|
if line[0] == ".logic_tile":
|
|
self.logic_tiles[(int(line[1]), int(line[2]))] = current_data
|
|
continue
|
|
if line[0] == ".ramb_tile":
|
|
self.ramb_tiles[(int(line[1]), int(line[2]))] = current_data
|
|
continue
|
|
if line[0] == ".ramt_tile":
|
|
self.ramt_tiles[(int(line[1]), int(line[2]))] = current_data
|
|
continue
|
|
if line[0] == ".ram_data":
|
|
self.ram_data[(int(line[1]), int(line[2]))] = current_data
|
|
continue
|
|
if line[0] == ".extra_bit":
|
|
self.extra_bits.add((int(line[1]), int(line[2]), int(line[3])))
|
|
continue
|
|
if line[0] == ".device":
|
|
assert line[1] in ["1k"]
|
|
self.device = line[1]
|
|
continue
|
|
if line[0] in [".comment", ".sym"]:
|
|
expected_data_lines = -1
|
|
continue
|
|
print("%sWarning: ignoring line %d: %s" % (logprefix, linenum, linetext.strip()))
|
|
expected_data_lines = -1
|
|
|
|
class tileconfig:
|
|
def __init__(self, tile):
|
|
self.bits = set()
|
|
for k, line in enumerate(tile):
|
|
for i in range(len(line)):
|
|
if line[i] == "1":
|
|
self.bits.add("B%d[%d]" % (k, i))
|
|
else:
|
|
self.bits.add("!B%d[%d]" % (k, i))
|
|
def match(self, pattern):
|
|
for bit in pattern:
|
|
if not bit in self.bits:
|
|
return False
|
|
return True
|
|
|
|
if False:
|
|
## Lattice span net name normalization
|
|
|
|
valid_sp4_h_l = set([1, 2, 4, 5, 7, 9, 10, 11, 15, 16, 17, 21, 24, 34, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47])
|
|
valid_sp4_h_r = set([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 19, 21, 24, 25, 27, 30, 31, 33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46])
|
|
|
|
valid_sp4_v_t = set([1, 3, 5, 9, 12, 14, 16, 17, 18, 21, 22, 23, 26, 28, 29, 30, 32, 33, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47])
|
|
valid_sp4_v_b = set([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 18, 19, 21, 22, 23, 24, 26, 30, 33, 36, 37, 38, 42, 46, 47])
|
|
|
|
valid_sp12_h_l = set([3, 4, 5, 12, 14, 16, 17, 18, 21, 22, 23])
|
|
valid_sp12_h_r = set([0, 1, 2, 3, 5, 8, 9, 10, 11, 12, 13, 14, 16, 20, 23])
|
|
|
|
valid_sp12_v_t = set([0, 1, 2, 3, 6, 9, 10, 12, 14, 21, 22, 23])
|
|
valid_sp12_v_b = set([0, 1, 6, 7, 8, 11, 12, 14, 16, 18, 19, 20, 21, 23])
|
|
|
|
else:
|
|
## IceStorm span net name normalization
|
|
|
|
valid_sp4_h_l = set(range(36, 48))
|
|
valid_sp4_h_r = set(range(48))
|
|
|
|
valid_sp4_v_t = set(range(36, 48))
|
|
valid_sp4_v_b = set(range(48))
|
|
|
|
valid_sp12_h_l = set(range(22, 24))
|
|
valid_sp12_h_r = set(range(24))
|
|
|
|
valid_sp12_v_t = set(range(22, 24))
|
|
valid_sp12_v_b = set(range(24))
|
|
|
|
def sp4h_normalize(netname, edge=""):
|
|
m = re.match("sp4_h_([lr])_(\d+)$", netname)
|
|
assert m
|
|
if not m: return None
|
|
cur_edge = m.group(1)
|
|
cur_index = int(m.group(2))
|
|
|
|
if cur_edge == edge:
|
|
return netname
|
|
|
|
if cur_edge == "r" and (edge == "l" or (edge == "" and cur_index not in valid_sp4_h_r)):
|
|
if cur_index < 12:
|
|
return None
|
|
return "sp4_h_l_%d" % ((cur_index-12)^1)
|
|
|
|
if cur_edge == "l" and (edge == "r" or (edge == "" and cur_index not in valid_sp4_h_l)):
|
|
if cur_index >= 36:
|
|
return None
|
|
return "sp4_h_r_%d" % ((cur_index+12)^1)
|
|
|
|
return netname
|
|
|
|
def sp4v_normalize(netname, edge=""):
|
|
m = re.match("sp4_v_([bt])_(\d+)$", netname)
|
|
assert m
|
|
if not m: return None
|
|
cur_edge = m.group(1)
|
|
cur_index = int(m.group(2))
|
|
|
|
if cur_edge == edge:
|
|
return netname
|
|
|
|
if cur_edge == "b" and (edge == "t" or (edge == "" and cur_index not in valid_sp4_v_b)):
|
|
if cur_index < 12:
|
|
return None
|
|
return "sp4_v_t_%d" % ((cur_index-12)^1)
|
|
|
|
if cur_edge == "t" and (edge == "b" or (edge == "" and cur_index not in valid_sp4_v_t)):
|
|
if cur_index >= 36:
|
|
return None
|
|
return "sp4_v_b_%d" % ((cur_index+12)^1)
|
|
|
|
return netname
|
|
|
|
def sp12h_normalize(netname, edge=""):
|
|
m = re.match("sp12_h_([lr])_(\d+)$", netname)
|
|
assert m
|
|
if not m: return None
|
|
cur_edge = m.group(1)
|
|
cur_index = int(m.group(2))
|
|
|
|
if cur_edge == edge:
|
|
return netname
|
|
|
|
if cur_edge == "r" and (edge == "l" or (edge == "" and cur_index not in valid_sp12_h_r)):
|
|
if cur_index < 2:
|
|
return None
|
|
return "sp12_h_l_%d" % ((cur_index-2)^1)
|
|
|
|
if cur_edge == "l" and (edge == "r" or (edge == "" and cur_index not in valid_sp12_h_l)):
|
|
if cur_index >= 22:
|
|
return None
|
|
return "sp12_h_r_%d" % ((cur_index+2)^1)
|
|
|
|
return netname
|
|
|
|
def sp12v_normalize(netname, edge=""):
|
|
m = re.match("sp12_v_([bt])_(\d+)$", netname)
|
|
assert m
|
|
if not m: return None
|
|
cur_edge = m.group(1)
|
|
cur_index = int(m.group(2))
|
|
|
|
if cur_edge == edge:
|
|
return netname
|
|
|
|
if cur_edge == "b" and (edge == "t" or (edge == "" and cur_index not in valid_sp12_v_b)):
|
|
if cur_index < 2:
|
|
return None
|
|
return "sp12_v_t_%d" % ((cur_index-2)^1)
|
|
|
|
if cur_edge == "t" and (edge == "b" or (edge == "" and cur_index not in valid_sp12_v_t)):
|
|
if cur_index >= 22:
|
|
return None
|
|
return "sp12_v_b_%d" % ((cur_index+2)^1)
|
|
|
|
return netname
|
|
|
|
def netname_normalize(netname, edge="", ramb=False, ramt=False):
|
|
if netname.startswith("sp4_v_"): return sp4v_normalize(netname, edge)
|
|
if netname.startswith("sp4_h_"): return sp4h_normalize(netname, edge)
|
|
if netname.startswith("sp12_v_"): return sp12v_normalize(netname, edge)
|
|
if netname.startswith("sp12_h_"): return sp12h_normalize(netname, edge)
|
|
if netname.startswith("input_2_"): netname = netname.replace("input_2_", "wire_logic_cluster/lc_") + "/in_2"
|
|
netname = netname.replace("lc_trk_", "local_")
|
|
netname = netname.replace("lc_", "lutff_")
|
|
netname = netname.replace("wire_logic_cluster/", "")
|
|
netname = netname.replace("wire_io_cluster/", "")
|
|
netname = netname.replace("wire_bram/", "")
|
|
if (ramb or ramt) and netname.startswith("input"):
|
|
match = re.match(r"input(\d)_(\d)", netname)
|
|
idx1, idx2 = (int(match.group(1)), int(match.group(2)))
|
|
if ramb: netname="ram/WADDR_%d" % (idx1*4 + idx2)
|
|
if ramt: netname="ram/RADDR_%d" % (idx1*4 + idx2)
|
|
match = re.match(r"(...)_op_(.*)", netname)
|
|
if match:
|
|
netname = "neigh_op_%s_%s" % (match.group(1), match.group(2))
|
|
if re.match(r"lutff_7/(cen|clk|s_r)", netname):
|
|
netname = netname.replace("lutff_7/", "lutff_global/")
|
|
if re.match(r"io_1/(cen|inclk|outclk)", netname):
|
|
netname = netname.replace("io_1/", "io_global/")
|
|
if netname == "carry_in_mux/cout":
|
|
return "carry_in_mux"
|
|
return netname
|
|
|
|
def pos_has_net(pos, netname):
|
|
if pos in ("l", "r"):
|
|
if re.search(r"_vert_\d+$", netname): return False
|
|
if re.search(r"_horz_[rl]_\d+$", netname): return False
|
|
if pos in ("t", "b"):
|
|
if re.search(r"_horz_\d+$", netname): return False
|
|
if re.search(r"_vert_[bt]_\d+$", netname): return False
|
|
return True
|
|
|
|
def pos_follow_net(pos, direction, netname):
|
|
if pos == "x":
|
|
m = re.match("sp4_h_[lr]_(\d+)$", netname)
|
|
if m and direction in ("l", "L"):
|
|
n = sp4h_normalize(netname, "l")
|
|
if n is not None:
|
|
if direction == "l":
|
|
n = re.sub("_l_", "_r_", n)
|
|
n = sp4h_normalize(n)
|
|
else:
|
|
n = re.sub("_l_", "_", n)
|
|
n = re.sub("sp4_h_", "span4_horz_", n)
|
|
return n
|
|
if m and direction in ("r", "R"):
|
|
n = sp4h_normalize(netname, "r")
|
|
if n is not None:
|
|
if direction == "r":
|
|
n = re.sub("_r_", "_l_", n)
|
|
n = sp4h_normalize(n)
|
|
else:
|
|
n = re.sub("_r_", "_", n)
|
|
n = re.sub("sp4_h_", "span4_horz_", n)
|
|
return n
|
|
|
|
m = re.match("sp4_v_[tb]_(\d+)$", netname)
|
|
if m and direction in ("t", "T"):
|
|
n = sp4v_normalize(netname, "t")
|
|
if n is not None:
|
|
if direction == "t":
|
|
n = re.sub("_t_", "_b_", n)
|
|
n = sp4v_normalize(n)
|
|
else:
|
|
n = re.sub("_t_", "_", n)
|
|
n = re.sub("sp4_v_", "span4_vert_", n)
|
|
return n
|
|
if m and direction in ("b", "B"):
|
|
n = sp4v_normalize(netname, "b")
|
|
if n is not None:
|
|
if direction == "b":
|
|
n = re.sub("_b_", "_t_", n)
|
|
n = sp4v_normalize(n)
|
|
else:
|
|
n = re.sub("_b_", "_", n)
|
|
n = re.sub("sp4_v_", "span4_vert_", n)
|
|
return n
|
|
|
|
m = re.match("sp12_h_[lr]_(\d+)$", netname)
|
|
if m and direction in ("l", "L"):
|
|
n = sp12h_normalize(netname, "l")
|
|
if n is not None:
|
|
if direction == "l":
|
|
n = re.sub("_l_", "_r_", n)
|
|
n = sp12h_normalize(n)
|
|
else:
|
|
n = re.sub("_l_", "_", n)
|
|
n = re.sub("sp12_h_", "span12_horz_", n)
|
|
return n
|
|
if m and direction in ("r", "R"):
|
|
n = sp12h_normalize(netname, "r")
|
|
if n is not None:
|
|
if direction == "r":
|
|
n = re.sub("_r_", "_l_", n)
|
|
n = sp12h_normalize(n)
|
|
else:
|
|
n = re.sub("_r_", "_", n)
|
|
n = re.sub("sp12_h_", "span12_horz_", n)
|
|
return n
|
|
|
|
m = re.match("sp12_v_[tb]_(\d+)$", netname)
|
|
if m and direction in ("t", "T"):
|
|
n = sp12v_normalize(netname, "t")
|
|
if n is not None:
|
|
if direction == "t":
|
|
n = re.sub("_t_", "_b_", n)
|
|
n = sp12v_normalize(n)
|
|
else:
|
|
n = re.sub("_t_", "_", n)
|
|
n = re.sub("sp12_v_", "span12_vert_", n)
|
|
return n
|
|
if m and direction in ("b", "B"):
|
|
n = sp12v_normalize(netname, "b")
|
|
if n is not None:
|
|
if direction == "b":
|
|
n = re.sub("_b_", "_t_", n)
|
|
n = sp12v_normalize(n)
|
|
else:
|
|
n = re.sub("_b_", "_", n)
|
|
n = re.sub("sp12_v_", "span12_vert_", n)
|
|
return n
|
|
|
|
if pos in ("l", "r" ):
|
|
m = re.match("span4_vert_([bt])_(\d+)$", netname)
|
|
if m:
|
|
case, idx = direction + m.group(1), int(m.group(2))
|
|
if case == "tt":
|
|
return "span4_vert_b_%d" % idx
|
|
if case == "tb" and idx >= 4:
|
|
return "span4_vert_b_%d" % (idx-4)
|
|
if case == "bb" and idx < 12:
|
|
return "span4_vert_b_%d" % (idx+4)
|
|
if case == "bb" and idx >= 12:
|
|
return "span4_vert_t_%d" % idx
|
|
|
|
if pos in ("t", "b" ):
|
|
m = re.match("span4_horz_([rl])_(\d+)$", netname)
|
|
if m:
|
|
case, idx = direction + m.group(1), int(m.group(2))
|
|
if case == "ll":
|
|
return "span4_horz_r_%d" % idx
|
|
if case == "lr" and idx >= 4:
|
|
return "span4_horz_r_%d" % (idx-4)
|
|
if case == "rr" and idx < 12:
|
|
return "span4_horz_r_%d" % (idx+4)
|
|
if case == "rr" and idx >= 12:
|
|
return "span4_horz_l_%d" % idx
|
|
|
|
if pos == "l" and direction == "r":
|
|
m = re.match("span4_horz_(\d+)$", netname)
|
|
if m: return sp4h_normalize("sp4_h_l_%s" % m.group(1))
|
|
m = re.match("span12_horz_(\d+)$", netname)
|
|
if m: return sp12h_normalize("sp12_h_l_%s" % m.group(1))
|
|
|
|
if pos == "r" and direction == "l":
|
|
m = re.match("span4_horz_(\d+)$", netname)
|
|
if m: return sp4h_normalize("sp4_h_r_%s" % m.group(1))
|
|
m = re.match("span12_horz_(\d+)$", netname)
|
|
if m: return sp12h_normalize("sp12_h_r_%s" % m.group(1))
|
|
|
|
if pos == "t" and direction == "b":
|
|
m = re.match("span4_vert_(\d+)$", netname)
|
|
if m: return sp4v_normalize("sp4_v_t_%s" % m.group(1))
|
|
m = re.match("span12_vert_(\d+)$", netname)
|
|
if m: return sp12v_normalize("sp12_v_t_%s" % m.group(1))
|
|
|
|
if pos == "b" and direction == "t":
|
|
m = re.match("span4_vert_(\d+)$", netname)
|
|
if m: return sp4v_normalize("sp4_v_b_%s" % m.group(1))
|
|
m = re.match("span12_vert_(\d+)$", netname)
|
|
if m: return sp12v_normalize("sp12_v_b_%s" % m.group(1))
|
|
|
|
return None
|
|
|
|
def get_lutff_bits(tile, index):
|
|
bits = list("--------------------")
|
|
for k, line in enumerate(tile):
|
|
for i in range(36, 46):
|
|
lutff_idx = k // 2
|
|
lutff_bitnum = (i-36) + 10*(k%2)
|
|
if lutff_idx == index:
|
|
bits[lutff_bitnum] = line[i];
|
|
return bits
|
|
|
|
def get_lutff_lut_bits(tile, index):
|
|
lutff_bits = get_lutff_bits(tile, index)
|
|
return [lutff_bits[i] for i in [4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0]]
|
|
|
|
def get_lutff_seq_bits(tile, index):
|
|
lutff_bits = get_lutff_bits(tile, index)
|
|
return [lutff_bits[i] for i in [8, 9, 18, 19]]
|
|
|
|
def get_carry_cascade_bit(tile):
|
|
return tile[1][49]
|
|
|
|
def get_carry_bit(tile):
|
|
return tile[1][50]
|
|
|
|
def get_negclk_bit(tile):
|
|
return tile[0][0]
|
|
|
|
def cmp_netnames(a, b):
|
|
a = re.sub(r"\d+", lambda m: "%09d" % int(m.group(0)), a)
|
|
b = re.sub(r"\d+", lambda m: "%09d" % int(m.group(0)), b)
|
|
return cmp(a, b)
|
|
|
|
def run_checks_neigh():
|
|
print("Running consistency checks on neighbour finder..")
|
|
ic = iceconfig()
|
|
ic.setup_empty_1k()
|
|
|
|
all_segments = set()
|
|
|
|
def add_segments(idx, db):
|
|
for entry in db:
|
|
if entry[1] in ("routing", "buffer"):
|
|
if not ic.tile_has_net(idx[0], idx[1], entry[2]): continue
|
|
if not ic.tile_has_net(idx[0], idx[1], entry[3]): continue
|
|
all_segments.add((idx[0], idx[1], entry[2]))
|
|
all_segments.add((idx[0], idx[1], entry[3]))
|
|
|
|
for x in range(ic.max_x+1):
|
|
for y in range(ic.max_x+1):
|
|
if x in (0, ic.max_x) and y in (0, ic.max_y):
|
|
continue
|
|
if x in (0, ic.max_x) or y in (0, ic.max_y):
|
|
add_segments((x, y), ic.tile_db(x, y))
|
|
elif (x, y) in ic.ramb_tiles:
|
|
add_segments((x, y), ic.tile_db(x, y))
|
|
elif (x, y) in ic.ramt_tiles:
|
|
add_segments((x, y), ic.tile_db(x, y))
|
|
else:
|
|
add_segments((x, y), logictile_db)
|
|
all_segments.add((x, y, "lutff_7/cout"))
|
|
|
|
for s1 in all_segments:
|
|
for s2 in ic.follow_net(s1):
|
|
if s1 not in ic.follow_net(s2):
|
|
print("ERROR: %s -> %s, but not vice versa!" % (s1, s2))
|
|
print("Neighbours of %s:" % (s1,))
|
|
for s in ic.follow_net(s1):
|
|
print(" ", s)
|
|
print("Neighbours of %s:" % (s2,))
|
|
for s in ic.follow_net(s2):
|
|
print(" ", s)
|
|
print()
|
|
|
|
def run_checks():
|
|
run_checks_neigh()
|
|
|
|
def parse_db(text):
|
|
db = list()
|
|
for line in text.split("\n"):
|
|
line = line.split("\t")
|
|
if len(line) == 0 or line[0] == "":
|
|
continue
|
|
line[0] = line[0].split(",")
|
|
db.append(line)
|
|
return db
|
|
|
|
extra_bits_db = {
|
|
"1k": {
|
|
(0, 330, 142): ("padin_glb_netwk", "0"),
|
|
(0, 331, 142): ("padin_glb_netwk", "1"),
|
|
(1, 330, 143): ("padin_glb_netwk", "2"),
|
|
(1, 331, 143): ("padin_glb_netwk", "3"),
|
|
(1, 330, 142): ("padin_glb_netwk", "4"),
|
|
(1, 331, 142): ("padin_glb_netwk", "5"),
|
|
(0, 330, 143): ("padin_glb_netwk", "6"),
|
|
(0, 331, 143): ("padin_glb_netwk", "7"),
|
|
}
|
|
}
|
|
|
|
gbufin_db = {
|
|
"1k": [
|
|
(13, 8, 7),
|
|
( 0, 8, 6),
|
|
( 7, 17, 1),
|
|
( 7, 0, 0),
|
|
( 0, 9, 3),
|
|
(13, 9, 2),
|
|
( 6, 0, 5),
|
|
( 6, 17, 4),
|
|
]
|
|
}
|
|
|
|
iolatch_db = {
|
|
"1k": [
|
|
( 0, 7),
|
|
(13, 10),
|
|
( 5, 0),
|
|
( 8, 17)
|
|
]
|
|
}
|
|
|
|
pllinfo_db = {
|
|
"1k": {
|
|
"SHIFTREG_DIV_MODE": (0, 3, "B2[2]"),
|
|
"FDA_FEEDBACK_0": (0, 3, "B7[3]"),
|
|
"FDA_FEEDBACK_1": (0, 4, "B0[2]"),
|
|
"FDA_FEEDBACK_2": (0, 4, "B0[3]"),
|
|
"FDA_FEEDBACK_3": (0, 4, "B3[3]"),
|
|
"FDA_RELATIVE_0": (0, 4, "B2[3]"),
|
|
"FDA_RELATIVE_1": (0, 4, "B5[3]"),
|
|
"FDA_RELATIVE_2": (0, 4, "B4[2]"),
|
|
"FDA_RELATIVE_3": (0, 4, "B4[3]"),
|
|
"DIVR_0": (0, 1, "B0[2]"),
|
|
"DIVR_1": (0, 1, "B0[3]"),
|
|
"DIVR_2": (0, 1, "B3[3]"),
|
|
"DIVR_3": (0, 1, "B2[2]"),
|
|
"DIVF_0": (0, 1, "B2[3]"),
|
|
"DIVF_1": (0, 1, "B5[3]"),
|
|
"DIVF_2": (0, 1, "B4[2]"),
|
|
"DIVF_3": (0, 1, "B4[3]"),
|
|
"DIVF_4": (0, 1, "B7[3]"),
|
|
"DIVF_5": (0, 2, "B0[2]"),
|
|
"DIVF_6": (0, 2, "B0[3]"),
|
|
"DIVQ_0": (0, 0, "?"),
|
|
"DIVQ_1": (0, 0, "?"),
|
|
"DIVQ_2": (0, 0, "?"),
|
|
"FILTER_RANGE_0": (0, 2, "B5[3]"),
|
|
"FILTER_RANGE_1": (0, 2, "B4[2]"),
|
|
"FILTER_RANGE_2": (0, 2, "B4[3]"),
|
|
"ENABLE_ICEGATE": (0, 0, "?"),
|
|
"TEST_MODE": (0, 3, "B4[3]"),
|
|
}
|
|
}
|
|
|
|
padin_pio_db = {
|
|
"1k": [
|
|
(13, 8, 1), # glb_netwk_0
|
|
( 0, 8, 1), # glb_netwk_1
|
|
( 7, 17, 0), # glb_netwk_2
|
|
( 7, 0, 0), # glb_netwk_3
|
|
( 0, 9, 0), # glb_netwk_4
|
|
(13, 9, 0), # glb_netwk_5
|
|
( 6, 0, 1), # glb_netwk_6
|
|
( 6, 17, 1), # glb_netwk_7
|
|
]
|
|
}
|
|
|
|
ieren_db = {
|
|
"1k": [
|
|
# IO-block (X, Y, Z) <-> IeRen-block (X, Y, Z)
|
|
( 0, 14, 1, 0, 14, 0),
|
|
( 0, 14, 0, 0, 14, 1),
|
|
( 0, 13, 1, 0, 13, 0),
|
|
( 0, 13, 0, 0, 13, 1),
|
|
( 0, 12, 1, 0, 12, 0),
|
|
( 0, 12, 0, 0, 12, 1),
|
|
( 0, 11, 1, 0, 11, 0),
|
|
( 0, 11, 0, 0, 11, 1),
|
|
( 0, 10, 1, 0, 10, 0),
|
|
( 0, 10, 0, 0, 10, 1),
|
|
( 0, 9, 1, 0, 9, 0),
|
|
( 0, 9, 0, 0, 9, 1),
|
|
( 0, 8, 1, 0, 8, 0),
|
|
( 0, 8, 0, 0, 8, 1),
|
|
( 0, 6, 1, 0, 6, 0),
|
|
( 0, 6, 0, 0, 6, 1),
|
|
( 0, 5, 1, 0, 5, 0),
|
|
( 0, 5, 0, 0, 5, 1),
|
|
( 0, 4, 1, 0, 4, 0),
|
|
( 0, 4, 0, 0, 4, 1),
|
|
( 0, 3, 1, 0, 3, 0),
|
|
( 0, 3, 0, 0, 3, 1),
|
|
( 0, 2, 1, 0, 2, 0),
|
|
( 0, 2, 0, 0, 2, 1),
|
|
( 1, 0, 0, 1, 0, 0),
|
|
( 1, 0, 1, 1, 0, 1),
|
|
( 2, 0, 0, 2, 0, 0),
|
|
( 2, 0, 1, 2, 0, 1),
|
|
( 3, 0, 0, 3, 0, 0),
|
|
( 3, 0, 1, 3, 0, 1),
|
|
( 4, 0, 0, 4, 0, 0),
|
|
( 4, 0, 1, 4, 0, 1),
|
|
( 5, 0, 0, 5, 0, 0),
|
|
( 5, 0, 1, 5, 0, 1),
|
|
( 6, 0, 1, 6, 0, 0),
|
|
( 7, 0, 0, 6, 0, 1),
|
|
( 6, 0, 0, 7, 0, 0),
|
|
( 7, 0, 1, 7, 0, 1),
|
|
( 8, 0, 0, 8, 0, 0),
|
|
( 8, 0, 1, 8, 0, 1),
|
|
( 9, 0, 0, 9, 0, 0),
|
|
( 9, 0, 1, 9, 0, 1),
|
|
(10, 0, 0, 10, 0, 0),
|
|
(10, 0, 1, 10, 0, 1),
|
|
(11, 0, 0, 11, 0, 0),
|
|
(11, 0, 1, 11, 0, 1),
|
|
(12, 0, 0, 12, 0, 0),
|
|
(12, 0, 1, 12, 0, 1),
|
|
(13, 1, 0, 13, 1, 0),
|
|
(13, 1, 1, 13, 1, 1),
|
|
(13, 2, 0, 13, 2, 0),
|
|
(13, 2, 1, 13, 2, 1),
|
|
(13, 3, 1, 13, 3, 1),
|
|
(13, 4, 0, 13, 4, 0),
|
|
(13, 4, 1, 13, 4, 1),
|
|
(13, 6, 0, 13, 6, 0),
|
|
(13, 6, 1, 13, 6, 1),
|
|
(13, 7, 0, 13, 7, 0),
|
|
(13, 7, 1, 13, 7, 1),
|
|
(13, 8, 0, 13, 8, 0),
|
|
(13, 8, 1, 13, 8, 1),
|
|
(13, 9, 0, 13, 9, 0),
|
|
(13, 9, 1, 13, 9, 1),
|
|
(13, 11, 0, 13, 10, 0),
|
|
(13, 11, 1, 13, 10, 1),
|
|
(13, 12, 0, 13, 11, 0),
|
|
(13, 12, 1, 13, 11, 1),
|
|
(13, 13, 0, 13, 13, 0),
|
|
(13, 13, 1, 13, 13, 1),
|
|
(13, 14, 0, 13, 14, 0),
|
|
(13, 14, 1, 13, 14, 1),
|
|
(13, 15, 0, 13, 15, 0),
|
|
(13, 15, 1, 13, 15, 1),
|
|
(12, 17, 1, 12, 17, 1),
|
|
(12, 17, 0, 12, 17, 0),
|
|
(11, 17, 1, 11, 17, 1),
|
|
(11, 17, 0, 11, 17, 0),
|
|
(10, 17, 1, 9, 17, 1),
|
|
(10, 17, 0, 9, 17, 0),
|
|
( 9, 17, 1, 10, 17, 1),
|
|
( 9, 17, 0, 10, 17, 0),
|
|
( 8, 17, 1, 8, 17, 1),
|
|
( 8, 17, 0, 8, 17, 0),
|
|
( 7, 17, 1, 7, 17, 1),
|
|
( 7, 17, 0, 7, 17, 0),
|
|
( 6, 17, 1, 6, 17, 1),
|
|
( 5, 17, 1, 5, 17, 1),
|
|
( 5, 17, 0, 5, 17, 0),
|
|
( 4, 17, 1, 4, 17, 1),
|
|
( 4, 17, 0, 4, 17, 0),
|
|
( 3, 17, 1, 3, 17, 1),
|
|
( 3, 17, 0, 3, 17, 0),
|
|
( 2, 17, 1, 2, 17, 1),
|
|
( 2, 17, 0, 2, 17, 0),
|
|
( 1, 17, 1, 1, 17, 1),
|
|
( 1, 17, 0, 1, 17, 0)
|
|
]
|
|
}
|
|
|
|
iotile_full_db = parse_db(iceboxdb.database_io_txt)
|
|
logictile_db = parse_db(iceboxdb.database_logic_txt)
|
|
rambtile_db = parse_db(iceboxdb.database_ramb_txt)
|
|
ramttile_db = parse_db(iceboxdb.database_ramt_txt)
|
|
pinloc_db = [[int(s) for s in line.split()] for line in iceboxdb.pinloc_txt.split("\n") if line != ""]
|
|
|
|
iotile_l_db = list()
|
|
iotile_r_db = list()
|
|
iotile_t_db = list()
|
|
iotile_b_db = list()
|
|
|
|
for entry in iotile_full_db:
|
|
if entry[1] == "buffer" and entry[2].startswith("IO_L."):
|
|
new_entry = entry[:]
|
|
new_entry[2] = new_entry[2][5:]
|
|
iotile_l_db.append(new_entry)
|
|
elif entry[1] == "buffer" and entry[2].startswith("IO_R."):
|
|
new_entry = entry[:]
|
|
new_entry[2] = new_entry[2][5:]
|
|
iotile_r_db.append(new_entry)
|
|
elif entry[1] == "buffer" and entry[2].startswith("IO_T."):
|
|
new_entry = entry[:]
|
|
new_entry[2] = new_entry[2][5:]
|
|
iotile_t_db.append(new_entry)
|
|
elif entry[1] == "buffer" and entry[2].startswith("IO_B."):
|
|
new_entry = entry[:]
|
|
new_entry[2] = new_entry[2][5:]
|
|
iotile_b_db.append(new_entry)
|
|
else:
|
|
iotile_l_db.append(entry)
|
|
iotile_r_db.append(entry)
|
|
iotile_t_db.append(entry)
|
|
iotile_b_db.append(entry)
|
|
|
|
logictile_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"])
|
|
logictile_db.append([["B1[50]"], "CarryInSet"])
|
|
|
|
for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, rambtile_db, ramttile_db]:
|
|
for entry in db:
|
|
if entry[1] in ("buffer", "routing"):
|
|
entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db))
|
|
entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db))
|
|
unique_entries = dict()
|
|
while db:
|
|
entry = db.pop()
|
|
key = " ".join(entry[1:]) + str(entry)
|
|
unique_entries[key] = entry
|
|
for key in sorted(unique_entries):
|
|
db.append(unique_entries[key])
|
|
|
|
if __name__ == "__main__":
|
|
run_checks()
|
|
|