mirror of https://github.com/YosysHQ/icestorm.git
33 lines
595 B
Verilog
33 lines
595 B
Verilog
module top (
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inout [7:0] pin,
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input latch_in,
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input clk_en,
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input clk_in,
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input clk_out,
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input oen,
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input dout_0,
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input dout_1,
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output [7:0] din_0,
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output [7:0] din_1,
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output [7:0] globals
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);
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SB_GB_IO #(
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.PIN_TYPE(6'b 1100_00),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0),
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.IO_STANDARD("SB_LVCMOS")
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) PINS [7:0] (
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.PACKAGE_PIN(pin),
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.LATCH_INPUT_VALUE(latch_in),
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.CLOCK_ENABLE(clk_en),
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.INPUT_CLK(clk_in),
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.OUTPUT_CLK(clk_out),
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.OUTPUT_ENABLE(oen),
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.D_OUT_0(dout_0),
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.D_OUT_1(dout_1),
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.D_IN_0(din_0),
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.D_IN_1(din_1),
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.GLOBAL_BUFFER_OUTPUT(globals)
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);
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endmodule
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