mirror of https://github.com/YosysHQ/icestorm.git
43 lines
897 B
Verilog
43 lines
897 B
Verilog
module top (
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inout [7:0] pin,
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input in,
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output out
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);
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wire [7:0] glbl, clk;
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reg [7:0] q;
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SB_GB_IO #(
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.PIN_TYPE(6'b 0000_11),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0),
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.IO_STANDARD("SB_LVCMOS")
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) PIO[7:0] (
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.PACKAGE_PIN(pin),
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.LATCH_INPUT_VALUE(1'b1),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1(),
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.GLOBAL_BUFFER_OUTPUT(glbl)
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);
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assign clk[0] = glbl[0]; // glb_netwk_4
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assign clk[1] = glbl[1]; // glb_netwk_1
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assign clk[2] = glbl[2]; // glb_netwk_6
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assign clk[3] = glbl[3]; // glb_netwk_3
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assign clk[4] = glbl[4]; // glb_netwk_0
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assign clk[5] = glbl[5]; // glb_netwk_5
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assign clk[6] = glbl[6]; // glb_netwk_2
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assign clk[7] = glbl[7]; // glb_netwk_7
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genvar i;
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generate for (i = 0; i < 8; i=i+1) begin
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always @(posedge clk[i]) q[i] <= in;
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end endgenerate
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assign out = ^{q, in};
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endmodule
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