mirror of https://github.com/YosysHQ/icestorm.git
80 lines
3.0 KiB
ReStructuredText
80 lines
3.0 KiB
ReStructuredText
RAM Tile Documentation
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======================
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Span-4 and Span-12 Wires
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------------------------
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Regarding the Span-4 and Span-12 Wires a RAM tile behaves exactly like a
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LOGIC tile. So for simple applications that do not need the block ram
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resources, the RAM tiles can be handled like a LOGIC tiles without logic
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cells in them.
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Block RAM Resources
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-------------------
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A pair or RAM tiles (odd and even y-coordinates) provides an interface
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to a block ram cell. Like with LOGIC tiles, signals entering the RAM
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tile have to be routed over local tracks to the block ram inputs. Tiles
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with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles
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with even y-coordinates are "top" RAM Tiles (RAMT Tiles). Each pair of
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RAMB/RAMT tiles implements a SB_RAM40_4K cell. The cell ports are spread
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out over the two tiles as follows:
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=========== =========== ===========
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SB_RAM40_4K RAMB Tile RAMT Tile
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=========== =========== ===========
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RDATA[15:0] RDATA[7:0] RDATA[15:8]
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RADDR[10:0] -- RADDR[10:0]
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WADDR[10:0] WADDR[10:0] --
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MASK[15:0] MASK[7:0] MASK[15:8]
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WDATA[15:0] WDATA[7:0] WDATA[15:8]
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RCLKE -- RCLKE
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RCLK -- RCLK
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RE -- RE
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WCLKE WCLKE --
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WCLK WCLK --
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WE WE --
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=========== =========== ===========
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The configuration bit RamConfig PowerUp in the RAMB tile enables the
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memory. This bit is active-low in 1k chips, i.e. an unused RAM block has
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only this bit set. Note that icebox_explain.py will ignore all RAMB
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tiles that only have the RamConfig PowerUp bit set.
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In 8k chips the RamConfig PowerUp bit is active-high. So an unused RAM
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block has all bits cleared in the 8k config bitstream.
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The RamConfig CBIT\_\* bits in the RAMT tile configure the read/write
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width of the memory. Those bits map to the SB_RAM40_4K cell parameters
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as follows:
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============= ================
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SB_RAM40_4K RAMT Config Bit
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============= ================
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WRITE_MODE[0] RamConfig CBIT_0
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WRITE_MODE[1] RamConfig CBIT_1
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READ_MODE[0] RamConfig CBIT_2
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READ_MODE[1] RamConfig CBIT_3
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============= ================
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The read/write mode selects the width of the read/write port:
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==== ========== ====================================================
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MODE DATA Width Used WDATA/RDATA Bits
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==== ========== ====================================================
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0 16 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
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1 8 14, 12, 10, 8, 6, 4, 2, 0
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2 4 13, 9, 5, 1
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3 2 11, 3
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==== ========== ====================================================
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The NegClk bit in the RAMB tile (1k die) or RAMT tile (other devices)
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negates the polarity of the WCLK port, and the NegClk bit in the RAMT
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(1k die) or RAMB tile (other devices) tile negates the polarity of the
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RCLK port.
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A logic tile sends the output of its eight logic cells to its neighbour
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tiles. A RAM tile does the same thing with the RDATA outputs. Each RAMB
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tile exports its RDATA[7:0] outputs and each RAMT tile exports its
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RDATA[15:8] outputs via this mechanism.
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