Improved colbufs test case

icefuzz/tests/colbufs.pcf

@@ -1,8 +1,14 @@
-set_io clk[0] J3
-set_io clk[1] G1
-set_io clk[2] R9
-set_io clk[3] F7
-set_io clk[4] K9
-set_io clk[5] C8
-set_io clk[6] H11
-set_io clk[7] H16
+# set_io clk[0] J3
+# set_io clk[1] G1
+# set_io clk[2] R9
+# set_io clk[3] F7
+# set_io clk[4] K9
+# set_io clk[5] C8
+# set_io clk[6] H11
+# set_io clk[7] H16
+
+set_io clk[0] H16
+
+set_location bitslice[0].ram40_upper 8 11 0
+set_location bitslice[0].ram40_lower 25 5 0
+

icefuzz/tests/colbufs.v

@@ -1,18 +1,17 @@
 module top #(
-	parameter NUM_BITS = 8
+	parameter NUM_BITS = 1
 ) (
 	input [NUM_BITS-1:0] clk,
-	output reg [NUM_BITS-1:0] y
+	output [NUM_BITS-1:0] y
 );
-	wire [NUM_BITS-1:0] t1;
-	reg [NUM_BITS-1:0] t2;
+	wire [NUM_BITS-1:0] t1, t2, t3;
 
 	genvar i;
 	generate for (i = 0; i < NUM_BITS; i = i+1) begin:bitslice
 		SB_RAM40_4K #(
 			.READ_MODE(0),
 			.WRITE_MODE(0)
-		) ram40 (
+		) ram40_upper (
 			.WADDR(8'b0),
 			.RADDR(8'b0),
 			.MASK(~16'b0),
@@ -26,9 +25,35 @@ module top #(
 			.RCLK(clk[i])
 		);
 
-		always @(posedge clk[i]) begin
-			t2[i] <= t1[i];
-			y[i] <= t2[i];
-		end
+		SB_RAM40_4K #(
+			.READ_MODE(0),
+			.WRITE_MODE(0)
+		) ram40_lower (
+			.WADDR(8'b0),
+			.RADDR(8'b0),
+			.MASK(~16'b0),
+			.WDATA(8'b0),
+			.RDATA(t2[i]),
+			.WE(1'b1),
+			.WCLKE(1'b1),
+			.WCLK(clk[i]),
+			.RE(1'b1),
+			.RCLKE(1'b1),
+			.RCLK(clk[i])
+		);
+
+		SB_DFF dff (
+			.C(clk[i]),
+			.D(t1[i] ^ t2[i]),
+			.Q(t3[i])
+		);
+
+		SB_IO #(
+			.PIN_TYPE(6'b 0101_01)
+		) out (
+			.PACKAGE_PIN(y[i]),
+			.OUTPUT_CLK(clk[i]),
+			.D_OUT_0(t3[i])
+		);
 	end endgenerate
 endmodule