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Merge pull request #161 from mithro/lut-bit-defaults 

icebox_hlc2asc: Set LUT bits to zero by default.
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Clifford Wolf 2018-06-16 20:24:55 +02:00 committed by GitHub
parent 492a337202 f1f9da2d5b
commit f029975152
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1 changed files with 2 additions and 2 deletions
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icebox/icebox_hlc2asc.py
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@ -825,7 +825,7 @@ class LogicCell:
def __init__(self, tile, index):
self.tile = tile
self.index = index
self.lut_bits = None
self.lut_bits = ['0'] * 16
self.seq_bits = ['0'] * 4
def read(self, fields):
@ -841,7 +841,7 @@ class LogicCell:
if m < 16:
lut_bits = (16-m) * "0" + lut_bits
# Verilog 16'bXXXX is MSB first but the bitstream wants LSB.
self.lut_bits = lut_bits[::-1]
self.lut_bits = list(lut_bits[::-1])
else:
self.lut_bits = logic_expression_to_lut(
' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3'))