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Figure out missing SPI config bits, and add to chipdb

This commit is contained in:
David Shah 2017-11-29 12:37:40 +00:00
parent 411bcc53ff
commit ec3ad58683
3 changed files with 18 additions and 2 deletions
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8
icebox/icebox.py
View File

@ -4862,6 +4862,10 @@ extra_cells_db = {
"SOE": (0, 20, "slf_op_5"), "SOE": (0, 20, "slf_op_5"),
"SPIIRQ": (0, 20, "slf_op_2"), "SPIIRQ": (0, 20, "slf_op_2"),
"SPIWKUP": (0, 20, "slf_op_3"), "SPIWKUP": (0, 20, "slf_op_3"),
"SPI_ENABLE_0": (7, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_1": (7, 0, "cbit2usealt_in_1"),
"SPI_ENABLE_2": (6, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_3": (6, 0, "cbit2usealt_in_1"),
}, },
("SPI", (25, 0, 1)): { ("SPI", (25, 0, 1)): {
"MCSNO0": (25, 21, "slf_op_2"), "MCSNO0": (25, 21, "slf_op_2"),
@ -4912,6 +4916,10 @@ extra_cells_db = {
"SOE": (25, 20, "slf_op_5"), "SOE": (25, 20, "slf_op_5"),
"SPIIRQ": (25, 20, "slf_op_2"), "SPIIRQ": (25, 20, "slf_op_2"),
"SPIWKUP": (25, 20, "slf_op_3"), "SPIWKUP": (25, 20, "slf_op_3"),
"SPI_ENABLE_0": (23, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_1": (24, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_2": (23, 0, "cbit2usealt_in_1"),
"SPI_ENABLE_3": (24, 0, "cbit2usealt_in_1"),
}, },
("LEDDA_IP", (0, 31, 2)): { ("LEDDA_IP", (0, 31, 2)): {
"LEDDADDR0": (0, 28, "lutff_4/in_0"), "LEDDADDR0": (0, 28, "lutff_4/in_0"),

4
icefuzz/tests/ip/up5k_I2C_data.txt
View File

@ -43,8 +43,8 @@
("I2C", (25, 31, 0)): { ("I2C", (25, 31, 0)): {
"I2CIRQ": (25, 30, "slf_op_7"), "I2CIRQ": (25, 30, "slf_op_7"),
"I2CWKUP": (25, 29, "slf_op_5"), "I2CWKUP": (25, 29, "slf_op_5"),
"I2C_ENABLE_0": (19, 31, "cbit2usealt_in_0"), "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_1"),
"I2C_ENABLE_1": (19, 31, "cbit2usealt_in_1"), "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_0"),
"SBACKO": (25, 30, "slf_op_6"), "SBACKO": (25, 30, "slf_op_6"),
"SBADRI0": (25, 30, "lutff_1/in_0"), "SBADRI0": (25, 30, "lutff_1/in_0"),
"SBADRI1": (25, 30, "lutff_2/in_0"), "SBADRI1": (25, 30, "lutff_2/in_0"),

8
icefuzz/tests/ip/up5k_SPI_data.txt
View File

@ -47,6 +47,10 @@
"SOE": (0, 20, "slf_op_5"), "SOE": (0, 20, "slf_op_5"),
"SPIIRQ": (0, 20, "slf_op_2"), "SPIIRQ": (0, 20, "slf_op_2"),
"SPIWKUP": (0, 20, "slf_op_3"), "SPIWKUP": (0, 20, "slf_op_3"),
"SPI_ENABLE_0": (7, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_1": (7, 0, "cbit2usealt_in_1"),
"SPI_ENABLE_2": (6, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_3": (6, 0, "cbit2usealt_in_1"),
}, },
("SPI", (25, 0, 1)): { ("SPI", (25, 0, 1)): {
"MCSNO0": (25, 21, "slf_op_2"), "MCSNO0": (25, 21, "slf_op_2"),
@ -97,4 +101,8 @@
"SOE": (25, 20, "slf_op_5"), "SOE": (25, 20, "slf_op_5"),
"SPIIRQ": (25, 20, "slf_op_2"), "SPIIRQ": (25, 20, "slf_op_2"),
"SPIWKUP": (25, 20, "slf_op_3"), "SPIWKUP": (25, 20, "slf_op_3"),
"SPI_ENABLE_0": (23, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_1": (24, 0, "cbit2usealt_in_0"),
"SPI_ENABLE_2": (23, 0, "cbit2usealt_in_1"),
"SPI_ENABLE_3": (24, 0, "cbit2usealt_in_1"),
}, },