mirror of https://github.com/YosysHQ/icestorm.git
icetime progress
This commit is contained in:
Clifford Wolf
parent
2a8c4b7e6c
commit
e4ed27a3ab
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@ -2,7 +2,7 @@
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#include <stdlib.h>
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#include <unistd.h>
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#include <assert.h>
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#include <string.h>
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#include <string.h>
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#include <stdarg.h>
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#include <functional>
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@ -32,7 +32,7 @@ struct net_segment_t
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net_segment_t(int x, int y, int net, std::string name) :
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x(x), y(y), net(net), name(name) { }
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bool operator<(const net_segment_t &other) const {
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if (x != other.x)
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return x < other.x;
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@ -52,7 +52,7 @@ std::set<int> used_nets;
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std::set<net_segment_t> interconn_src, interconn_dst;
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std::set<int> no_interconn_net;
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int iconn_cell_cnt = 0;
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int tname_cnt = 0;
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// netlist_cells[cell_name][port_name] = port_expr
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std::map<std::string, std::map<std::string, std::string>> netlist_cells;
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@ -108,17 +108,24 @@ std::string stringf(const char *fmt, ...)
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return string;
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}
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std::string tname()
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{
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return stringf("t%d", tname_cnt++);
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}
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std::string net_name(int net)
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{
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declared_nets.insert(net);
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return stringf("net_%d", net);
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}
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std::string seg_name(const net_segment_t &seg)
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std::string seg_name(const net_segment_t &seg, int idx = 0)
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{
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std::string str = stringf("seg_%d_%d_%s_%d", seg.x, seg.y, seg.name.c_str(), seg.net);
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for (auto &ch : str)
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if (ch == '/') ch = '_';
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if (idx != 0)
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str += stringf("_i%d", idx);
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extra_wires.insert(str);
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return str;
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}
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@ -544,7 +551,7 @@ std::string make_lc40(int x, int y, int z)
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lcbits[i] = config_bits[x][y][lcbits_pos[i].first][lcbits_pos[i].second] ? '1' : '0';
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// FIXME: fill in the '0'
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netlist_cell_params[cell]["C_ON"] = stringf("1'b%c", '0');
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netlist_cell_params[cell]["C_ON"] = stringf("1'b%c", lcbits[8]);
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netlist_cell_params[cell]["SEQ_MODE"] = stringf("4'b%c%c%c%c", lcbits[9], '0', '0', '0');
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netlist_cell_params[cell]["LUT_INIT"] = stringf("16'b%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
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lcbits[0], lcbits[10], lcbits[11], lcbits[1],
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@ -552,9 +559,62 @@ std::string make_lc40(int x, int y, int z)
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lcbits[7], lcbits[17], lcbits[16], lcbits[6],
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lcbits[5], lcbits[15], lcbits[14], lcbits[4]);
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if (lcbits[8] == '1')
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{
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if (z == 0)
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{
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auto co_cell = make_lc40(x, y-1, 7);
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std::string n1, n2;
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char cinit_1 = config_bits[x][y][1][49] ? '1' : '0';
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char cinit_0 = config_bits[x][y][1][50] ? '1' : '0';
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if (cinit_1 == '1') {
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std::tuple<int, int, std::string> key(x, y-1, "lutff_7/cout");
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if (x_y_name_net.count(key)) {
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n1 = net_name(x_y_name_net.at(key));
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} else {
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n1 = tname();
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netlist_cells[co_cell]["carryout"] = n1;
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extra_wires.insert(n1);
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}
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}
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std::tuple<int, int, std::string> key(x, y, "carry_in_mux");
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if (x_y_name_net.count(key)) {
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n2 = net_name(x_y_name_net.at(key));
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} else {
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n2 = tname();
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extra_wires.insert(n2);
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}
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extra_vlog.push_back(stringf(" ICE_CARRY_IN_MUX #(.C_INIT(2'b%c%c)) %s (.carryinitin(%s), "
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".carryinitout(%s));\n", cinit_1, cinit_0, tname().c_str(), n1.c_str(), n2.c_str()));
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netlist_cells[cell]["carryin"] = n2;
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}
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else
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{
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auto co_cell = make_lc40(x, y, z-1);
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std::tuple<int, int, std::string> key(x, y, stringf("lutff_%d/cout", z-1));
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auto n = x_y_name_net.count(key) ? net_name(x_y_name_net.at(key)) : tname();
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netlist_cells[co_cell]["carryout"] = n;
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netlist_cells[cell]["carryin"] = n;
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extra_wires.insert(n);
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}
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std::tuple<int, int, std::string> key(x, y, stringf("lutff_%d/cout", z-1));
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}
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return cell;
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}
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bool dff_uses_clock(int x, int y, int z)
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{
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auto bitpos = logic_tile_bits[stringf("LC_%d", z)][9];
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return config_bits[x][y][bitpos.first][bitpos.second];
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}
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void make_odrv(int x, int y, int src)
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{
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for (int dst : net_buffers[src])
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@ -643,8 +703,8 @@ void make_seg_cell(int net, const net_segment_t &seg)
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if (b == 2) {
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// Lattice tools always put a CascadeMux on in2
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extra_wires.insert(net_name(net) + "_cascademuxed");
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extra_vlog.push_back(stringf(" CascadeMux conn_%d (.I(%s), .O(%s));\n",
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iconn_cell_cnt++, net_name(net).c_str(), (net_name(net) + "_cascademuxed").c_str()));
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extra_vlog.push_back(stringf(" CascadeMux %s (.I(%s), .O(%s));\n",
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tname().c_str(), net_name(net).c_str(), (net_name(net) + "_cascademuxed").c_str()));
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netlist_cells[cell][stringf("in%d", b)] = net_name(net) + "_cascademuxed";
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} else {
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netlist_cells[cell][stringf("in%d", b)] = net_name(net);
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@ -682,6 +742,9 @@ void make_seg_cell(int net, const net_segment_t &seg)
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{
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for (int i = 0; i < 8; i++)
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{
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if (!dff_uses_clock(seg.x, seg.y, i))
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continue;
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std::tuple<int, int, std::string> key(seg.x, seg.y, stringf("lutff_%d/out", i));
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if (x_y_name_net.count(key)) {
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auto cell = make_lc40(seg.x, seg.y, i);
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@ -699,6 +762,7 @@ struct make_interconn_worker_t
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std::map<net_segment_t, std::set<net_segment_t>> seg_tree;
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std::map<net_segment_t, net_segment_t> seg_parents;
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std::set<net_segment_t> target_segs, handled_segs;
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std::set<int> handled_global_nets;
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void build_net_tree(int src)
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{
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@ -801,7 +865,7 @@ struct make_interconn_worker_t
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void create_cells(const net_segment_t &trg)
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{
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if (handled_segs.count(trg))
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if (handled_segs.count(trg) || handled_global_nets.count(trg.net))
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return;
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handled_segs.insert(trg);
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@ -817,8 +881,8 @@ struct make_interconn_worker_t
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if (trg.name.substr(0, 6) == "local_")
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{
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extra_vlog.push_back(stringf(" LocalMux conn_%d (.I(%s), .O(%s));\n",
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iconn_cell_cnt++, seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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extra_vlog.push_back(stringf(" LocalMux %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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goto continue_at_cursor;
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}
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@ -839,15 +903,15 @@ struct make_interconn_worker_t
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goto skip_to_cursor;
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if (cursor->name.substr(0, 7) == "span12_" || cursor->name.substr(0, 5) == "sp12_") {
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extra_vlog.push_back(stringf(" Sp12to4 conn_%d (.I(%s), .O(%s));\n",
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iconn_cell_cnt++, seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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extra_vlog.push_back(stringf(" Sp12to4 %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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} else
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if (cursor->name.substr(0, 6) == "span4_") {
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extra_vlog.push_back(stringf(" IoSpan4Mux conn_%d (.I(%s), .O(%s));\n",
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iconn_cell_cnt++, seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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extra_vlog.push_back(stringf(" IoSpan4Mux %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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} else {
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extra_vlog.push_back(stringf(" Span4Mux_%c%d conn_%d (.I(%s), .O(%s));\n",
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horiz ? 'h' : 'v', count_length, iconn_cell_cnt++,
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extra_vlog.push_back(stringf(" Span4Mux_%c%d %s (.I(%s), .O(%s));\n",
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horiz ? 'h' : 'v', count_length, tname().c_str(),
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seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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}
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@ -870,23 +934,49 @@ struct make_interconn_worker_t
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if (cursor->net == trg.net)
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goto skip_to_cursor;
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extra_vlog.push_back(stringf(" Span12Mux_%c%d conn_%d (.I(%s), .O(%s));\n",
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horiz ? 'h' : 'v', count_length, iconn_cell_cnt++,
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extra_vlog.push_back(stringf(" Span12Mux_%c%d %s (.I(%s), .O(%s));\n",
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horiz ? 'h' : 'v', count_length, tname().c_str(),
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seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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goto continue_at_cursor;
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}
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// Global nets
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if (trg.name.substr(0, 10) == "glb_netwk_")
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{
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while (seg_parents.count(*cursor) && (cursor->net == trg.net || cursor->name == "fabout"))
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cursor = &seg_parents.at(*cursor);
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if (cursor->net == trg.net)
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goto skip_to_cursor;
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extra_vlog.push_back(stringf(" GlobalMux %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor, 3).c_str(), seg_name(trg).c_str()));
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extra_vlog.push_back(stringf(" gio2CtrlBuf %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor, 2).c_str(), seg_name(*cursor, 3).c_str()));
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extra_vlog.push_back(stringf(" ICE_GB %s (.USERSIGNALTOGLOBALBUFFER(%s), .GLOBALBUFFEROUTPUT(%s));\n",
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tname().c_str(), seg_name(*cursor, 1).c_str(), seg_name(*cursor, 2).c_str()));
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extra_vlog.push_back(stringf(" IoInMux %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor).c_str(), seg_name(*cursor, 1).c_str()));
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handled_global_nets.insert(trg.net);
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goto continue_at_cursor;
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}
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// Default handler
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while (seg_parents.count(*cursor))
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while (seg_parents.count(*cursor) && cursor->net == trg.net)
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cursor = &seg_parents.at(*cursor);
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if (cursor->net == trg.net)
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goto skip_to_cursor;
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extra_vlog.push_back(stringf(" INTERCONN conn_%d (.I(%s), .O(%s));\n",
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iconn_cell_cnt++, seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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extra_vlog.push_back(stringf(" INTERCONN %s (.I(%s), .O(%s));\n",
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tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
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goto continue_at_cursor;
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skip_to_cursor:
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@ -17,10 +17,9 @@ with open("%s.v" % sys.argv[1], "w") as f:
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if mode == "test0":
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io_names = [ "clk", "i0", "o0", "o1", "o2" ]
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print("module top(input clk, i0, output o0, o1, o2);", file=f)
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print(" reg [3:0] state;", file=f)
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# print(" always @(posedge clk) state <= (state << 7) ^ (state >> 13) ^ i0;", file=f)
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print(" always @(posedge clk) state <= (state << 1) ^ i0;", file=f)
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print(" assign o0 = ^state, o1 = |state, o2 = &state;", file=f)
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print(" reg [31:0] state;", file=f)
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print(" always @(posedge clk) state <= ((state << 5) + state) ^ i0;", file=f)
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print(" assign o0 = ^state, o1 = |state, o2 = state[31:16] + state[15:0];", file=f)
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print("endmodule", file=f)
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if mode == "test1":
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io_names = [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3" ]
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@ -42,10 +41,11 @@ with open("%s.ys" % sys.argv[1], "w") as f:
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print("read_verilog %s_out.v" % sys.argv[1], file=f)
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print("prep", file=f)
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print("equiv_make top chip equiv", file=f)
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print("hierarchy -top equiv", file=f)
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print("cd equiv", file=f)
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print("script %s.lc" % sys.argv[1], file=f)
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print("rename -hide w:N_*", file=f)
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print("equiv_struct", file=f)
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print("opt_clean", file=f)
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print("opt_clean -purge", file=f)
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print("write_ilang %s.il" % sys.argv[1], file=f)
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print("equiv_status -assert", file=f)
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@ -97,6 +97,9 @@ with open("%s_ref.v" % sys.argv[1], "w") as f:
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f.write(line)
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assert os.system("yosys -qp 'select -write %s.lc t:LogicCell40' %s_ref.v" % (sys.argv[1], sys.argv[1])) == 0
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assert os.system(r"sed -i -r 's,.*/(.*)LC_(.*),equiv_add -cell \1LC_\2_gold lc40_\2_gate,' %s.lc" % sys.argv[1]) == 0
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os.remove("%s.bin" % sys.argv[1])
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os.remove("%s.vsb" % sys.argv[1])
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os.remove("%s.glb" % sys.argv[1])
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