mirror of https://github.com/YosysHQ/icestorm.git
icetime progress
This commit is contained in:
Clifford Wolf
parent
986b644d96
commit
d939d1b92f
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@ -80,13 +80,14 @@ std::set<net_segment_t> interconn_src, interconn_dst;
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std::set<int> no_interconn_net;
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int tname_cnt = 0;
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// netlist_cells[cell_name][port_name] = port_expr
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std::map<std::string, std::map<std::string, std::string>> netlist_cells;
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// netlist_cell_ports[cell_name][port_name] = port_expr
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std::map<std::string, std::map<std::string, std::string>> netlist_cell_ports;
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std::map<std::string, std::map<std::string, std::string>> netlist_cell_params;
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std::map<std::string, std::string> netlist_cell_types;
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std::set<std::string> extra_wires;
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std::vector<std::string> extra_vlog;
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std::map<std::string, std::string> net_assignments;
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std::set<int> declared_nets;
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int dangling_cnt = 0;
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@ -479,6 +480,240 @@ void read_chipdb()
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#endif
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}
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bool is_primary(std::string cell_name, std::string out_port)
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{
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return false;
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}
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const std::set<std::string> &get_inports(std::string cell_type)
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{
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static bool first_call = true;
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static std::map<std::string, std::set<std::string>> inports_map;
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if (first_call)
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{
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first_call = false;
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inports_map["Span4Mux_h0"] = { "I" };
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inports_map["Span4Mux_h1"] = { "I" };
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inports_map["Span4Mux_h2"] = { "I" };
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inports_map["Span4Mux_h3"] = { "I" };
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inports_map["Span4Mux_h4"] = { "I" };
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inports_map["Span4Mux_v0"] = { "I" };
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inports_map["Span4Mux_v1"] = { "I" };
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inports_map["Span4Mux_v2"] = { "I" };
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inports_map["Span4Mux_v3"] = { "I" };
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inports_map["Span4Mux_v4"] = { "I" };
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inports_map["Span12Mux_h0"] = { "I" };
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inports_map["Span12Mux_h1"] = { "I" };
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inports_map["Span12Mux_h2"] = { "I" };
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inports_map["Span12Mux_h3"] = { "I" };
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inports_map["Span12Mux_h4"] = { "I" };
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inports_map["Span12Mux_h5"] = { "I" };
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inports_map["Span12Mux_h6"] = { "I" };
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inports_map["Span12Mux_h7"] = { "I" };
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inports_map["Span12Mux_h8"] = { "I" };
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inports_map["Span12Mux_h9"] = { "I" };
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inports_map["Span12Mux_h10"] = { "I" };
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inports_map["Span12Mux_h11"] = { "I" };
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inports_map["Span12Mux_h12"] = { "I" };
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inports_map["Span12Mux_v0"] = { "I" };
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inports_map["Span12Mux_v1"] = { "I" };
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inports_map["Span12Mux_v2"] = { "I" };
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inports_map["Span12Mux_v3"] = { "I" };
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inports_map["Span12Mux_v4"] = { "I" };
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inports_map["Span12Mux_v5"] = { "I" };
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inports_map["Span12Mux_v6"] = { "I" };
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inports_map["Span12Mux_v7"] = { "I" };
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inports_map["Span12Mux_v8"] = { "I" };
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inports_map["Span12Mux_v9"] = { "I" };
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inports_map["Span12Mux_v10"] = { "I" };
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inports_map["Span12Mux_v11"] = { "I" };
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inports_map["Span12Mux_v12"] = { "I" };
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inports_map["Odrv4"] = { "I" };
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inports_map["Odrv12"] = { "I" };
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inports_map["Sp12to4"] = { "I" };
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inports_map["InMux"] = { "I" };
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inports_map["IoInMux"] = { "I" };
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inports_map["IoSpan4Mux"] = { "I" };
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inports_map["IpInMux"] = { "I" };
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inports_map["IpOutMux"] = { "I" };
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inports_map["LocalMux"] = { "I" };
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inports_map["CEMux"] = { "I" };
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inports_map["SRMux"] = { "I" };
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inports_map["ClkMux"] = { "I" };
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inports_map["CascadeBuf"] = { "I" };
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inports_map["CascadeMux"] = { "I" };
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inports_map["GlobalMux"] = { "I" };
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inports_map["gio2CtrlBuf"] = { "I" };
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inports_map["ICE_GB"] = { "USERSIGNALTOGLOBALBUFFER" };
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inports_map["ICE_CARRY_IN_MUX"] = { "carryinitin" };
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inports_map["LogicCell40"] = { "clk", "carryin", "in0", "in1", "in2", "in3", "sr", "ce" };
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inports_map["PRE_IO"] = { "INPUTCLK", "OUTPUTCLK", "LATCHINPUTVALUE", "CLOCKENABLE", "OUTPUTENABLE", "DOUT1", "DOUT0" };
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inports_map["SB_RAM40_4K"] = { "RCLK", "RCLKE", "RE", "WCLK", "WCLKE", "WE" };
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for (int i = 0; i < 16; i++) {
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inports_map["SB_RAM40_4K"].insert(stringf("MASK[%d]", i));
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inports_map["SB_RAM40_4K"].insert(stringf("WDATA[%d]", i));
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}
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for (int i = 0; i < 11; i++) {
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inports_map["SB_RAM40_4K"].insert(stringf("RADDR[%d]", i));
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inports_map["SB_RAM40_4K"].insert(stringf("WADDR[%d]", i));
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}
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}
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if (inports_map.count(cell_type) == 0) {
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fprintf(stderr, "Missing entry in inports_map for cell type %s!\n", cell_type.c_str());
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exit(1);
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}
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return inports_map.at(cell_type);
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}
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double get_delay(std::string cell_type, std::string in_port, std::string out_port)
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{
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return 1.0;
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}
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struct TimingAnalysis
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{
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// net_driver[<net_name>] = { <cell_name>, <cell_port> }
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std::map<std::string, std::pair<std::string, std::string>> net_driver;
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// net_max_path_parent[<net_name>] = { <parent_net>, <cell_name>, <inport>, <outport>, <delay> }
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std::map<std::string, std::tuple<std::string, std::string, std::string, std::string, double>> net_max_path_parent;
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std::map<std::string, double> net_max_path_delay;
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std::string global_max_path_net;
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double global_max_path_delay;
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double calc_net_max_path_delay(const std::string &net)
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{
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if (net_max_path_delay.count(net))
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return net_max_path_delay.at(net);
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if (net_driver.count(net) == 0)
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return 0;
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double max_path_delay = 0;
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net_max_path_delay[net] = 1e6;
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auto &driver_cell = net_driver.at(net).first;
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auto &driver_port = net_driver.at(net).second;
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if (is_primary(driver_cell, driver_port)) {
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net_max_path_delay[net] = 0;
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return 0;
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}
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auto &driver_type = netlist_cell_types.at(driver_cell);
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auto &driver_inputs = get_inports(driver_type);
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for (auto &inport : driver_inputs)
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{
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if (inport == "clk" || inport == "INPUTCLK" || inport == "OUTPUTCLK")
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continue;
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std::string *in_net = &netlist_cell_ports.at(driver_cell).at(inport);
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while (net_assignments.count(*in_net))
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in_net = &net_assignments.at(*in_net);
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if (*in_net == "" || *in_net == "vcc" || *in_net == "gnd")
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continue;
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double this_cell_delay = get_delay(driver_type, inport, driver_port);
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double this_path_delay = calc_net_max_path_delay(*in_net) + this_cell_delay;
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if (this_path_delay >= max_path_delay) {
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net_max_path_parent[net] = std::make_tuple(*in_net, driver_cell, inport, driver_port, this_cell_delay);
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max_path_delay = this_path_delay;
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}
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}
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net_max_path_delay[net] = max_path_delay;
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return net_max_path_delay.at(net);
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}
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TimingAnalysis()
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{
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std::set<std::string> all_nets;
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for (auto &it : netlist_cell_ports)
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for (auto &it2 : it.second)
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{
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auto &cell_name = it.first;
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auto &port_name = it2.first;
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auto &net_name = it2.second;
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if (net_name == "")
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continue;
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if (get_inports(netlist_cell_types.at(cell_name)).count(port_name))
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continue;
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net_driver[net_name] = { cell_name, port_name };
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all_nets.insert(net_name);
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}
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global_max_path_delay = 0;
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for (auto &net : all_nets) {
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double d = calc_net_max_path_delay(net);
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if (d > global_max_path_delay) {
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global_max_path_delay = d;
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global_max_path_net = net;
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}
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}
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}
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void report()
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{
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std::vector<std::string> lines;
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std::set<std::string> visited_nets;
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std::string n = global_max_path_net;
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bool last_line = true;
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while (1)
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{
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if (net_max_path_parent.count(n) == 0) {
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lines.push_back(stringf("%10.3f ns %s", calc_net_max_path_delay(n), n.c_str()));
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break;
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}
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if (visited_nets.count(n)) {
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lines.push_back(stringf("loop-start at %s", n.c_str()));
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break;
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}
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auto &entry = net_max_path_parent.at(n);
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if (last_line || netlist_cell_types.at(std::get<1>(entry)) == "LogicCell40")
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lines.push_back(stringf("%10.3f ns %s", calc_net_max_path_delay(n), n.c_str()));
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lines.push_back(stringf(" %s (%s) %s -> %s: %.3f ns", std::get<1>(entry).c_str(),
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netlist_cell_types.at(std::get<1>(entry)).c_str(), std::get<2>(entry).c_str(),
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std::get<3>(entry).c_str(), std::get<4>(entry)));
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visited_nets.insert(n);
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n = std::get<0>(entry);
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last_line = false;
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}
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for (int i = int(lines.size())-1; i >= 0; i--)
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printf("%s\n", lines[i].c_str());
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}
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};
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void register_interconn_src(int x, int y, int net)
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{
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std::tuple<int, int, int> key(x, y, net);
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@ -499,18 +734,18 @@ std::string make_seg_pre_io(int x, int y, int z)
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return cell;
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netlist_cell_types[cell] = "PRE_IO";
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netlist_cells[cell]["PADIN"] = stringf("io_pad_%d_%d_%d_dout", x, y, z);
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netlist_cells[cell]["PADOUT"] = stringf("io_pad_%d_%d_%d_din", x, y, z);
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netlist_cells[cell]["PADOEN"] = stringf("io_pad_%d_%d_%d_oe", x, y, z);
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netlist_cells[cell]["LATCHINPUTVALUE"] = "";
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netlist_cells[cell]["CLOCKENABLE"] = "";
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netlist_cells[cell]["INPUTCLK"] = "";
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netlist_cells[cell]["OUTPUTCLK"] = "";
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netlist_cells[cell]["OUTPUTENABLE"] = "";
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netlist_cells[cell]["DOUT1"] = "";
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netlist_cells[cell]["DOUT0"] = "";
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netlist_cells[cell]["DIN1"] = "";
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netlist_cells[cell]["DIN0"] = "";
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netlist_cell_ports[cell]["PADIN"] = stringf("io_pad_%d_%d_%d_dout", x, y, z);
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netlist_cell_ports[cell]["PADOUT"] = stringf("io_pad_%d_%d_%d_din", x, y, z);
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netlist_cell_ports[cell]["PADOEN"] = stringf("io_pad_%d_%d_%d_oe", x, y, z);
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netlist_cell_ports[cell]["LATCHINPUTVALUE"] = "";
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netlist_cell_ports[cell]["CLOCKENABLE"] = "";
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netlist_cell_ports[cell]["INPUTCLK"] = "";
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netlist_cell_ports[cell]["OUTPUTCLK"] = "";
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netlist_cell_ports[cell]["OUTPUTENABLE"] = "";
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netlist_cell_ports[cell]["DOUT1"] = "";
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netlist_cell_ports[cell]["DOUT0"] = "";
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netlist_cell_ports[cell]["DIN1"] = "";
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netlist_cell_ports[cell]["DIN0"] = "";
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std::string pintype;
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std::pair<int, int> bitpos;
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@ -559,17 +794,17 @@ std::string make_lc40(int x, int y, int z)
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return cell;
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netlist_cell_types[cell] = "LogicCell40";
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netlist_cells[cell]["carryin"] = "gnd";
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netlist_cells[cell]["ce"] = "";
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netlist_cells[cell]["clk"] = "gnd";
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netlist_cells[cell]["in0"] = "gnd";
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netlist_cells[cell]["in1"] = "gnd";
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netlist_cells[cell]["in2"] = "gnd";
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netlist_cells[cell]["in3"] = "gnd";
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netlist_cells[cell]["sr"] = "gnd";
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netlist_cells[cell]["carryout"] = "";
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netlist_cells[cell]["lcout"] = "";
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netlist_cells[cell]["ltout"] = "";
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netlist_cell_ports[cell]["carryin"] = "gnd";
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netlist_cell_ports[cell]["ce"] = "";
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netlist_cell_ports[cell]["clk"] = "gnd";
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netlist_cell_ports[cell]["in0"] = "gnd";
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netlist_cell_ports[cell]["in1"] = "gnd";
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netlist_cell_ports[cell]["in2"] = "gnd";
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netlist_cell_ports[cell]["in3"] = "gnd";
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netlist_cell_ports[cell]["sr"] = "gnd";
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netlist_cell_ports[cell]["carryout"] = "";
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netlist_cell_ports[cell]["lcout"] = "";
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netlist_cell_ports[cell]["ltout"] = "";
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char lcbits[20];
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auto &lcbits_pos = logic_tile_bits[stringf("LC_%d", z)];
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@ -602,7 +837,7 @@ std::string make_lc40(int x, int y, int z)
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n1 = net_name(x_y_name_net.at(key));
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} else {
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n1 = tname();
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netlist_cells[co_cell]["carryout"] = n1;
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netlist_cell_ports[co_cell]["carryout"] = n1;
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extra_wires.insert(n1);
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}
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}
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@ -615,9 +850,13 @@ std::string make_lc40(int x, int y, int z)
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extra_wires.insert(n2);
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}
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extra_vlog.push_back(stringf(" ICE_CARRY_IN_MUX #(.C_INIT(2'b%c%c)) %s (.carryinitin(%s), "
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".carryinitout(%s));\n", cinit_1, cinit_0, tname().c_str(), n1.c_str(), n2.c_str()));
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netlist_cells[cell]["carryin"] = n2;
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std::string tn = tname();
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netlist_cell_types[tn] = "ICE_CARRY_IN_MUX";
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netlist_cell_params[tn]["C_INIT"] = stringf("2'b%c%c", cinit_1, cinit_0);
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netlist_cell_ports[tn]["carryinitin"] = n1;
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netlist_cell_ports[tn]["carryinitout"] = n2;
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netlist_cell_ports[cell]["carryin"] = n2;
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}
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else
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{
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@ -625,8 +864,8 @@ std::string make_lc40(int x, int y, int z)
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std::tuple<int, int, std::string> key(x, y, stringf("lutff_%d/cout", z-1));
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auto n = x_y_name_net.count(key) ? net_name(x_y_name_net.at(key)) : tname();
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netlist_cells[co_cell]["carryout"] = n;
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netlist_cells[cell]["carryin"] = n;
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netlist_cell_ports[co_cell]["carryout"] = n;
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netlist_cell_ports[cell]["carryin"] = n;
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extra_wires.insert(n);
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}
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@ -646,23 +885,23 @@ std::string make_ram(int x, int y)
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netlist_cell_types[cell] = "SB_RAM40_4K";
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for (int i = 0; i < 16; i++) {
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netlist_cells[cell][stringf("MASK[%d]", i)] = "";
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netlist_cells[cell][stringf("RDATA[%d]", i)] = "";
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netlist_cells[cell][stringf("WDATA[%d]", i)] = "";
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netlist_cell_ports[cell][stringf("MASK[%d]", i)] = "";
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netlist_cell_ports[cell][stringf("RDATA[%d]", i)] = "";
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netlist_cell_ports[cell][stringf("WDATA[%d]", i)] = "";
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}
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for (int i = 0; i < 11; i++) {
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netlist_cells[cell][stringf("RADDR[%d]", i)] = "";
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netlist_cells[cell][stringf("WADDR[%d]", i)] = "";
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netlist_cell_ports[cell][stringf("RADDR[%d]", i)] = "";
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netlist_cell_ports[cell][stringf("WADDR[%d]", i)] = "";
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}
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netlist_cells[cell]["RE"] = "";
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netlist_cells[cell]["RCLK"] = "";
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netlist_cells[cell]["RCLKE"] = "";
|
||||
netlist_cell_ports[cell]["RE"] = "";
|
||||
netlist_cell_ports[cell]["RCLK"] = "";
|
||||
netlist_cell_ports[cell]["RCLKE"] = "";
|
||||
|
||||
netlist_cells[cell]["WE"] = "";
|
||||
netlist_cells[cell]["WCLK"] = "";
|
||||
netlist_cells[cell]["WCLKE"] = "";
|
||||
netlist_cell_ports[cell]["WE"] = "";
|
||||
netlist_cell_ports[cell]["WCLK"] = "";
|
||||
netlist_cell_ports[cell]["WCLKE"] = "";
|
||||
|
||||
return cell;
|
||||
}
|
||||
|
|
@ -698,8 +937,8 @@ void make_odrv(int x, int y, int src)
|
|||
|
||||
assert(is4 != is12);
|
||||
netlist_cell_types[cell] = is4 ? "Odrv4" : "Odrv12";
|
||||
netlist_cells[cell]["I"] = net_name(src);
|
||||
netlist_cells[cell]["O"] = net_name(dst);
|
||||
netlist_cell_ports[cell]["I"] = net_name(src);
|
||||
netlist_cell_ports[cell]["O"] = net_name(dst);
|
||||
register_interconn_src(x, y, dst);
|
||||
}
|
||||
}
|
||||
|
|
@ -719,7 +958,7 @@ void make_inmux(int x, int y, int dst, std::string muxtype = "")
|
|||
|
||||
if (src_name == "lutff_X/lout") {
|
||||
auto cell = make_lc40(x, y, cascade_n);
|
||||
netlist_cells[cell]["ltout"] = net_name(dst);
|
||||
netlist_cell_ports[cell]["ltout"] = net_name(dst);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -729,8 +968,8 @@ void make_inmux(int x, int y, int dst, std::string muxtype = "")
|
|||
continue;
|
||||
|
||||
netlist_cell_types[cell] = muxtype.empty() ? (config_tile_type[x][y] == "io" ? "IoInMux" : "InMux") : muxtype;
|
||||
netlist_cells[cell]["I"] = net_name(src);
|
||||
netlist_cells[cell]["O"] = net_name(dst);
|
||||
netlist_cell_ports[cell]["I"] = net_name(src);
|
||||
netlist_cell_ports[cell]["O"] = net_name(dst);
|
||||
|
||||
register_interconn_dst(x, y, src);
|
||||
no_interconn_net.insert(dst);
|
||||
|
|
@ -741,7 +980,12 @@ std::string cascademuxed(std::string n)
|
|||
{
|
||||
std::string nc = n + "_cascademuxed";
|
||||
extra_wires.insert(nc);
|
||||
extra_vlog.push_back(stringf(" CascadeMux %s (.I(%s), .O(%s));\n", tname().c_str(), n.c_str(), nc.c_str()));
|
||||
|
||||
std::string tn = tname();
|
||||
netlist_cell_types[tn] = "CascadeMux";
|
||||
netlist_cell_ports[tn]["I"] = n;
|
||||
netlist_cell_ports[tn]["O"] = nc;
|
||||
|
||||
return nc;
|
||||
}
|
||||
|
||||
|
|
@ -752,14 +996,14 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
|
||||
if (sscanf(seg.name.c_str(), "io_%d/D_IN_%d", &a, &b) == 2) {
|
||||
auto cell = make_seg_pre_io(seg.x, seg.y, a);
|
||||
netlist_cells[cell][stringf("DIN%d", b)] = net_name(net);
|
||||
netlist_cell_ports[cell][stringf("DIN%d", b)] = net_name(net);
|
||||
make_odrv(seg.x, seg.y, net);
|
||||
return;
|
||||
}
|
||||
|
||||
if (sscanf(seg.name.c_str(), "io_%d/D_OUT_%d", &a, &b) == 2) {
|
||||
auto cell = make_seg_pre_io(seg.x, seg.y, a);
|
||||
netlist_cells[cell][stringf("DOUT%d", b)] = net_name(net);
|
||||
netlist_cell_ports[cell][stringf("DOUT%d", b)] = net_name(net);
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
return;
|
||||
}
|
||||
|
|
@ -768,9 +1012,9 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
auto cell = make_lc40(seg.x, seg.y, a);
|
||||
if (b == 2) {
|
||||
// Lattice tools always put a CascadeMux on in2
|
||||
netlist_cells[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
|
||||
netlist_cell_ports[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
|
||||
} else {
|
||||
netlist_cells[cell][stringf("in%d", b)] = net_name(net);
|
||||
netlist_cell_ports[cell][stringf("in%d", b)] = net_name(net);
|
||||
}
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
return;
|
||||
|
|
@ -789,7 +1033,7 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
|
||||
use_lcout:
|
||||
auto cell = make_lc40(seg.x, seg.y, a);
|
||||
netlist_cells[cell]["lcout"] = net_name(net);
|
||||
netlist_cell_ports[cell]["lcout"] = net_name(net);
|
||||
make_odrv(seg.x, seg.y, net);
|
||||
return;
|
||||
}
|
||||
|
|
@ -797,7 +1041,7 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
if (sscanf(seg.name.c_str(), "lutff_%d/cou%c", &a, &c) == 2 && c == 't')
|
||||
{
|
||||
auto cell = make_lc40(seg.x, seg.y, a);
|
||||
netlist_cells[cell]["carryout"] = net_name(net);
|
||||
netlist_cell_ports[cell]["carryout"] = net_name(net);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -806,26 +1050,26 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
auto cell = make_ram(seg.x, 2*((seg.y-1) >> 1) + 1);
|
||||
|
||||
if (sscanf(seg.name.c_str(), "ram/MASK_%d", &a) == 1) {
|
||||
netlist_cells[cell][stringf("MASK[%d]", a)] = net_name(net);
|
||||
netlist_cell_ports[cell][stringf("MASK[%d]", a)] = net_name(net);
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
} else
|
||||
if (sscanf(seg.name.c_str(), "ram/RADDR_%d", &a) == 1) {
|
||||
netlist_cells[cell][stringf("RADDR[%d]", a)] = cascademuxed(net_name(net));
|
||||
netlist_cell_ports[cell][stringf("RADDR[%d]", a)] = cascademuxed(net_name(net));
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
} else
|
||||
if (sscanf(seg.name.c_str(), "ram/RDATA_%d", &a) == 1) {
|
||||
netlist_cells[cell][stringf("RDATA[%d]", a)] = net_name(net);
|
||||
netlist_cell_ports[cell][stringf("RDATA[%d]", a)] = net_name(net);
|
||||
make_odrv(seg.x, seg.y, net);
|
||||
} else
|
||||
if (sscanf(seg.name.c_str(), "ram/WADDR_%d", &a) == 1) {
|
||||
netlist_cells[cell][stringf("WADDR[%d]", a)] = cascademuxed(net_name(net));
|
||||
netlist_cell_ports[cell][stringf("WADDR[%d]", a)] = cascademuxed(net_name(net));
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
} else
|
||||
if (sscanf(seg.name.c_str(), "ram/WDATA_%d", &a) == 1) {
|
||||
netlist_cells[cell][stringf("WDATA[%d]", a)] = net_name(net);
|
||||
netlist_cell_ports[cell][stringf("WDATA[%d]", a)] = net_name(net);
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
} else {
|
||||
netlist_cells[cell][seg.name.substr(4)] = net_name(net);
|
||||
netlist_cell_ports[cell][seg.name.substr(4)] = net_name(net);
|
||||
if (seg.name == "ram/RCLK" || seg.name == "ram/WCLK")
|
||||
make_inmux(seg.x, seg.y, net, "ClkMux");
|
||||
else if (seg.name == "ram/RCLKE" || seg.name == "ram/WCLKE")
|
||||
|
|
@ -848,7 +1092,7 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
if (x_y_name_net.count(key)) {
|
||||
auto cell = make_lc40(seg.x, seg.y, i);
|
||||
make_inmux(seg.x, seg.y, net, "ClkMux");
|
||||
netlist_cells[cell]["clk"] = net_name(seg.net);
|
||||
netlist_cell_ports[cell]["clk"] = net_name(seg.net);
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
|
@ -898,21 +1142,21 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
auto cell = make_seg_pre_io(seg.x, seg.y, z);
|
||||
|
||||
if (seg.name == "io_global/inclk" && use_inclk) {
|
||||
netlist_cells[cell]["INPUTCLK"] = net_name(seg.net);
|
||||
netlist_cell_ports[cell]["INPUTCLK"] = net_name(seg.net);
|
||||
make_inmux(seg.x, seg.y, seg.net, "ClkMux");
|
||||
}
|
||||
|
||||
if (seg.name == "io_global/outclk" && use_outclk) {
|
||||
netlist_cells[cell]["OUTPUTCLK"] = net_name(seg.net);
|
||||
netlist_cell_ports[cell]["OUTPUTCLK"] = net_name(seg.net);
|
||||
make_inmux(seg.x, seg.y, seg.net, "ClkMux");
|
||||
}
|
||||
|
||||
if (seg.name == "io_global/cen") {
|
||||
netlist_cells[cell]["CLOCKENABLE"] = net_name(seg.net);
|
||||
netlist_cell_ports[cell]["CLOCKENABLE"] = net_name(seg.net);
|
||||
make_inmux(seg.x, seg.y, seg.net, "CEMux");
|
||||
} else {
|
||||
if (netlist_cells[cell]["CLOCKENABLE"] == "")
|
||||
netlist_cells[cell]["CLOCKENABLE"] = "vcc";
|
||||
if (netlist_cell_ports[cell]["CLOCKENABLE"] == "")
|
||||
netlist_cell_ports[cell]["CLOCKENABLE"] = "vcc";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1051,18 +1295,22 @@ struct make_interconn_worker_t
|
|||
handled_segs.insert(trg);
|
||||
|
||||
if (seg_parents.count(trg) == 0) {
|
||||
extra_vlog.push_back(stringf(" assign %s = %s;\n", seg_name(trg).c_str(), net_name(trg.net).c_str()));
|
||||
net_assignments[seg_name(trg)] = net_name(trg.net);
|
||||
return;
|
||||
}
|
||||
|
||||
const net_segment_t *cursor = &seg_parents.at(trg);
|
||||
std::string tn;
|
||||
|
||||
// Local Mux
|
||||
|
||||
if (trg.name.substr(0, 6) == "local_")
|
||||
{
|
||||
extra_vlog.push_back(stringf(" LocalMux %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "LocalMux";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
|
||||
cell_log[trg] = std::make_pair(*cursor, "LocalMux");
|
||||
goto continue_at_cursor;
|
||||
}
|
||||
|
|
@ -1086,18 +1334,23 @@ struct make_interconn_worker_t
|
|||
count_length = std::max(count_length, 0);
|
||||
|
||||
if (cursor->name.substr(0, 7) == "span12_" || cursor->name.substr(0, 5) == "sp12_") {
|
||||
extra_vlog.push_back(stringf(" Sp12to4 %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "Sp12to4";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
cell_log[trg] = std::make_pair(*cursor, "Sp12to4");
|
||||
} else
|
||||
if (cursor->name.substr(0, 6) == "span4_") {
|
||||
extra_vlog.push_back(stringf(" IoSpan4Mux %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "IoSpan4Mux";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
cell_log[trg] = std::make_pair(*cursor, "IoSpan4Mux");
|
||||
} else {
|
||||
extra_vlog.push_back(stringf(" Span4Mux_%c%d %s (.I(%s), .O(%s));\n",
|
||||
horiz ? 'h' : 'v', MAX_SPAN_HACK ? 4 : count_length, tname().c_str(),
|
||||
seg_name(*cursor).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = stringf("Span4Mux_%c%d", horiz ? 'h' : 'v', MAX_SPAN_HACK ? 4 : count_length);
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
cell_log[trg] = std::make_pair(*cursor, stringf("Span4Mux_%c%d", horiz ? 'h' : 'v', count_length));
|
||||
}
|
||||
|
||||
|
|
@ -1122,9 +1375,10 @@ struct make_interconn_worker_t
|
|||
|
||||
count_length = std::max(count_length, 0);
|
||||
|
||||
extra_vlog.push_back(stringf(" Span12Mux_%c%d %s (.I(%s), .O(%s));\n",
|
||||
horiz ? 'h' : 'v', MAX_SPAN_HACK ? 12 : count_length, tname().c_str(),
|
||||
seg_name(*cursor).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = stringf("Span12Mux_%c%d", horiz ? 'h' : 'v', MAX_SPAN_HACK ? 12 : count_length);
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
cell_log[trg] = std::make_pair(*cursor, stringf("Span12Mux_%c%d", horiz ? 'h' : 'v', count_length));
|
||||
|
||||
goto continue_at_cursor;
|
||||
|
|
@ -1140,17 +1394,25 @@ struct make_interconn_worker_t
|
|||
if (cursor->net == trg.net)
|
||||
goto skip_to_cursor;
|
||||
|
||||
extra_vlog.push_back(stringf(" GlobalMux %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor, 3).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "GlobalMux";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor, 3);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
|
||||
extra_vlog.push_back(stringf(" gio2CtrlBuf %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor, 2).c_str(), seg_name(*cursor, 3).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "gio2CtrlBuf";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor, 2);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(*cursor, 3);
|
||||
|
||||
extra_vlog.push_back(stringf(" ICE_GB %s (.USERSIGNALTOGLOBALBUFFER(%s), .GLOBALBUFFEROUTPUT(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor, 1).c_str(), seg_name(*cursor, 2).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "ICE_GB";
|
||||
netlist_cell_ports[tn]["USERSIGNALTOGLOBALBUFFER"] = seg_name(*cursor, 1);
|
||||
netlist_cell_ports[tn]["GLOBALBUFFEROUTPUT"] = seg_name(*cursor, 2);
|
||||
|
||||
extra_vlog.push_back(stringf(" IoInMux %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor).c_str(), seg_name(*cursor, 1).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "IoInMux";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(*cursor, 1);
|
||||
|
||||
cell_log[trg] = std::make_pair(*cursor, "GlobalMux -> ICE_GB -> IoInMux");
|
||||
|
||||
|
|
@ -1166,13 +1428,16 @@ struct make_interconn_worker_t
|
|||
if (cursor->net == trg.net)
|
||||
goto skip_to_cursor;
|
||||
|
||||
extra_vlog.push_back(stringf(" INTERCONN %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), seg_name(*cursor).c_str(), seg_name(trg).c_str()));
|
||||
tn = tname();
|
||||
netlist_cell_types[tn] = "INTERCONN";
|
||||
netlist_cell_ports[tn]["I"] = seg_name(*cursor);
|
||||
netlist_cell_ports[tn]["O"] = seg_name(trg);
|
||||
|
||||
cell_log[trg] = std::make_pair(*cursor, "INTERCONN");
|
||||
goto continue_at_cursor;
|
||||
|
||||
skip_to_cursor:
|
||||
extra_vlog.push_back(stringf(" assign %s = %s;\n", seg_name(trg).c_str(), seg_name(*cursor).c_str()));
|
||||
net_assignments[seg_name(trg)] = seg_name(*cursor);
|
||||
continue_at_cursor:
|
||||
create_cells(*cursor);
|
||||
}
|
||||
|
|
@ -1275,7 +1540,7 @@ void make_interconn(const net_segment_t &src, FILE *graph_f)
|
|||
#endif
|
||||
|
||||
for (auto &seg : worker.target_segs) {
|
||||
extra_vlog.push_back(stringf(" assign %s = %s;\n", net_name(seg.net).c_str(), seg_name(seg).c_str()));
|
||||
net_assignments[net_name(seg.net)] = seg_name(seg);
|
||||
worker.create_cells(seg);
|
||||
}
|
||||
|
||||
|
|
@ -1391,17 +1656,19 @@ int main(int argc, char **argv)
|
|||
{
|
||||
std::string port = stringf("WADDR[%d]", i);
|
||||
|
||||
if (netlist_cells[src_cell][port] == "")
|
||||
if (netlist_cell_ports[src_cell][port] == "")
|
||||
continue;
|
||||
|
||||
std::string srcnet = netlist_cells[src_cell][port];
|
||||
std::string srcnet = netlist_cell_ports[src_cell][port];
|
||||
std::string tmpnet = tname();
|
||||
extra_wires.insert(tmpnet);
|
||||
|
||||
extra_vlog.push_back(stringf(" CascadeBuf %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), srcnet.c_str(), tmpnet.c_str()));
|
||||
std::string tn = tname();
|
||||
netlist_cell_types[tn] = "CascadeBuf";
|
||||
netlist_cell_ports[tn]["I"] = srcnet;
|
||||
netlist_cell_ports[tn]["O"] = tmpnet;
|
||||
|
||||
netlist_cells[dst_cell][port] = cascademuxed(tmpnet);
|
||||
netlist_cell_ports[dst_cell][port] = cascademuxed(tmpnet);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1414,17 +1681,19 @@ int main(int argc, char **argv)
|
|||
{
|
||||
std::string port = stringf("RADDR[%d]", i);
|
||||
|
||||
if (netlist_cells[src_cell][port] == "")
|
||||
if (netlist_cell_ports[src_cell][port] == "")
|
||||
continue;
|
||||
|
||||
std::string srcnet = netlist_cells[src_cell][port];
|
||||
std::string srcnet = netlist_cell_ports[src_cell][port];
|
||||
std::string tmpnet = tname();
|
||||
extra_wires.insert(tmpnet);
|
||||
|
||||
extra_vlog.push_back(stringf(" CascadeBuf %s (.I(%s), .O(%s));\n",
|
||||
tname().c_str(), srcnet.c_str(), tmpnet.c_str()));
|
||||
std::string tn = tname();
|
||||
netlist_cell_types[tn] = "CascadeBuf";
|
||||
netlist_cell_ports[tn]["I"] = srcnet;
|
||||
netlist_cell_ports[tn]["O"] = tmpnet;
|
||||
|
||||
netlist_cells[dst_cell][port] = cascademuxed(tmpnet);
|
||||
netlist_cell_ports[dst_cell][port] = cascademuxed(tmpnet);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1453,7 +1722,7 @@ int main(int argc, char **argv)
|
|||
}
|
||||
|
||||
for (auto it : netlist_cell_types)
|
||||
for (auto &port : netlist_cells[it.first])
|
||||
for (auto &port : netlist_cell_ports[it.first])
|
||||
if (port.second == "") {
|
||||
size_t open_bracket_pos = port.first.find('[');
|
||||
if (open_bracket_pos == std::string::npos)
|
||||
|
|
@ -1475,6 +1744,9 @@ int main(int argc, char **argv)
|
|||
|
||||
for (auto net : extra_wires)
|
||||
fprintf(fout, " wire %s;\n", net.c_str());
|
||||
|
||||
for (auto &it : net_assignments)
|
||||
fprintf(fout, " assign %s = %s;\n", it.first.c_str(), it.second.c_str());
|
||||
|
||||
fprintf(fout, " wire gnd, vcc;\n");
|
||||
fprintf(fout, " GND gnd_cell (.Y(gnd));\n");
|
||||
|
|
@ -1500,7 +1772,7 @@ int main(int argc, char **argv)
|
|||
fprintf(fout, "%s (", it.first.c_str());
|
||||
std::map<std::string, std::vector<std::string>> multibit_ports;
|
||||
|
||||
for (auto port : netlist_cells[it.first])
|
||||
for (auto port : netlist_cell_ports[it.first])
|
||||
{
|
||||
size_t open_bracket_pos = port.first.find('[');
|
||||
if (open_bracket_pos != std::string::npos) {
|
||||
|
|
@ -1535,5 +1807,8 @@ int main(int argc, char **argv)
|
|||
|
||||
fprintf(fout, "endmodule\n");
|
||||
|
||||
TimingAnalysis ta;
|
||||
ta.report();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue