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Added tmedges

This commit is contained in:
Clifford Wolf 2015-09-27 11:54:43 +02:00
parent a110369832
commit d0f89d1bf1
4 changed files with 511 additions and 1 deletions
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6
icefuzz/Makefile
View File

@ -38,9 +38,15 @@ endif
timings:
ifeq ($(EIGTHK),_8k)
cp tmedges_8k.txt tmedges.tmp
for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
sort -u tmedges.tmp > tmedges_8k.txt && rm -f tmedges.tmp
python3 timings.py -t timings_8k.txt work_*/*.sdf > timings_8k.new
mv timings_8k.new timings_8k.txt
else
cp tmedges_1k.txt tmedges.tmp
for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
sort -u tmedges.tmp > tmedges_1k.txt && rm -f tmedges.tmp
python3 timings.py -t timings_1k.txt work_*/*.sdf > timings_1k.new
mv timings_1k.new timings_1k.txt
endif

3
icefuzz/timings.py
View File

@ -212,9 +212,10 @@ for filename in txt_inputs:
celltype = None
for line in f:
line = line.split()
if len(len) > 1:
if len(line) > 1:
if line[0] == "CELL":
celltype = line[1]
database.setdefault(celltype, set())
else:
database[celltype].add(tuple(line))

20
icefuzz/tmedges.ys Normal file
View File

@ -0,0 +1,20 @@
hierarchy -generate LogicCell40 i:in* i:*in i:clk i:ce i:sr o:*out
hierarchy -generate ICE_GB i:USERSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT
hierarchy -generate PRE_IO_GBUF i:PADSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT
hierarchy -generate VCC o:*
hierarchy -generate GND o:*
hierarchy -generate IO_PAD i:OE i:DIN o:DOUT io:PACKAGEPIN
hierarchy -generate PRE_IO o:PADOEN o:PADOUT i:PADIN i:CLOCKENABLE o:DIN0 o:DIN1 \
i:DOUT0 i:DOUT1 i:INPUTCLK i:LATCHINPUTVALUE i:OUTPUTCLK i:OUTPUTENABLE
hierarchy -generate *PLL40* i:PACKAGEPIN i:BYPASS i:DYNAMICDELAY i:EXTFEEDBACK i:LATCHINPUTVALUE \
o:LOCK o:PLLOUT* i:REFERENCECLK i:RESETB i:SCLK i:SDI o:SDO i:PLLIN
hierarchy -generate SB_RAM40_4K o:RDATA i:RADDR i:WADDR i:MASK i:WDATA i:RCLKE i:RCLK i:RE i:WCLKE i:WCLK i:WE
hierarchy -generate ICE_CARRY_IN_MUX i:*in o:*out
hierarchy -generate *Mux* i:I o:O
hierarchy -generate Odrv* i:I o:O
hierarchy -generate Sp12to4 i:I o:O
hierarchy -generate INV i:I o:O
hierarchy -generate gio2CtrlBuf i:I o:O
hierarchy -check
tee -a tmedges.tmp edgetypes

483
icefuzz/tmedges_1k.txt Normal file
View File

@ -0,0 +1,483 @@
CEMux.O LogicCell40.ce
CEMux.O PRE_IO.CLOCKENABLE
CEMux.O SB_RAM40_4K.RCLKE
CEMux.O SB_RAM40_4K.WCLKE
CascadeMux.O LogicCell40.in2
CascadeMux.O SB_RAM40_4K.RADDR[0]
CascadeMux.O SB_RAM40_4K.RADDR[10]
CascadeMux.O SB_RAM40_4K.RADDR[1]
CascadeMux.O SB_RAM40_4K.RADDR[2]
CascadeMux.O SB_RAM40_4K.RADDR[3]
CascadeMux.O SB_RAM40_4K.RADDR[4]
CascadeMux.O SB_RAM40_4K.RADDR[5]
CascadeMux.O SB_RAM40_4K.RADDR[6]
CascadeMux.O SB_RAM40_4K.RADDR[7]
CascadeMux.O SB_RAM40_4K.RADDR[8]
CascadeMux.O SB_RAM40_4K.RADDR[9]
CascadeMux.O SB_RAM40_4K.WADDR[0]
CascadeMux.O SB_RAM40_4K.WADDR[10]
CascadeMux.O SB_RAM40_4K.WADDR[1]
CascadeMux.O SB_RAM40_4K.WADDR[2]
CascadeMux.O SB_RAM40_4K.WADDR[3]
CascadeMux.O SB_RAM40_4K.WADDR[4]
CascadeMux.O SB_RAM40_4K.WADDR[5]
CascadeMux.O SB_RAM40_4K.WADDR[6]
CascadeMux.O SB_RAM40_4K.WADDR[7]
CascadeMux.O SB_RAM40_4K.WADDR[8]
CascadeMux.O SB_RAM40_4K.WADDR[9]
ClkMux.O INV.I
ClkMux.O LogicCell40.clk
ClkMux.O PRE_IO.INPUTCLK
ClkMux.O PRE_IO.OUTPUTCLK
ClkMux.O SB_RAM40_4K.RCLK
ClkMux.O SB_RAM40_4K.WCLK
GND.Y LogicCell40.carryin
GND.Y LogicCell40.clk
GND.Y LogicCell40.in0
GND.Y LogicCell40.in1
GND.Y LogicCell40.in2
GND.Y LogicCell40.in3
GND.Y LogicCell40.sr
GND.Y PRE_IO.DOUT0
Glb2LocalMux.O LocalMux.I
GlobalMux.O CEMux.I
GlobalMux.O ClkMux.I
GlobalMux.O Glb2LocalMux.I
GlobalMux.O SRMux.I
ICE_CARRY_IN_MUX.carryinitout InMux.I
ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin
ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
INV.O LogicCell40.clk
INV.O SB_RAM40_4K.RCLK
INV.O SB_RAM40_4K.WCLK
IO_PAD.DOUT PLL40.PLLIN
IO_PAD.DOUT PLL40_2.PLLIN
IO_PAD.DOUT PLL40_2F.PLLIN
IO_PAD.DOUT PRE_IO.PADIN
IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER
IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN
InMux.O CascadeMux.I
InMux.O LogicCell40.in0
InMux.O LogicCell40.in1
InMux.O LogicCell40.in3
InMux.O SB_RAM40_4K.MASK[0]
InMux.O SB_RAM40_4K.MASK[10]
InMux.O SB_RAM40_4K.MASK[11]
InMux.O SB_RAM40_4K.MASK[12]
InMux.O SB_RAM40_4K.MASK[13]
InMux.O SB_RAM40_4K.MASK[14]
InMux.O SB_RAM40_4K.MASK[15]
InMux.O SB_RAM40_4K.MASK[1]
InMux.O SB_RAM40_4K.MASK[2]
InMux.O SB_RAM40_4K.MASK[3]
InMux.O SB_RAM40_4K.MASK[4]
InMux.O SB_RAM40_4K.MASK[5]
InMux.O SB_RAM40_4K.MASK[6]
InMux.O SB_RAM40_4K.MASK[7]
InMux.O SB_RAM40_4K.MASK[8]
InMux.O SB_RAM40_4K.MASK[9]
InMux.O SB_RAM40_4K.WDATA[0]
InMux.O SB_RAM40_4K.WDATA[10]
InMux.O SB_RAM40_4K.WDATA[11]
InMux.O SB_RAM40_4K.WDATA[12]
InMux.O SB_RAM40_4K.WDATA[13]
InMux.O SB_RAM40_4K.WDATA[14]
InMux.O SB_RAM40_4K.WDATA[15]
InMux.O SB_RAM40_4K.WDATA[1]
InMux.O SB_RAM40_4K.WDATA[2]
InMux.O SB_RAM40_4K.WDATA[3]
InMux.O SB_RAM40_4K.WDATA[4]
InMux.O SB_RAM40_4K.WDATA[5]
InMux.O SB_RAM40_4K.WDATA[6]
InMux.O SB_RAM40_4K.WDATA[7]
InMux.O SB_RAM40_4K.WDATA[8]
InMux.O SB_RAM40_4K.WDATA[9]
IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER
IoInMux.O PLL40.BYPASS
IoInMux.O PLL40.DYNAMICDELAY[0]
IoInMux.O PLL40.DYNAMICDELAY[1]
IoInMux.O PLL40.DYNAMICDELAY[2]
IoInMux.O PLL40.DYNAMICDELAY[3]
IoInMux.O PLL40.DYNAMICDELAY[4]
IoInMux.O PLL40.DYNAMICDELAY[5]
IoInMux.O PLL40.DYNAMICDELAY[6]
IoInMux.O PLL40.DYNAMICDELAY[7]
IoInMux.O PLL40.EXTFEEDBACK
IoInMux.O PLL40.LATCHINPUTVALUE
IoInMux.O PLL40.RESETB
IoInMux.O PLL40.SCLK
IoInMux.O PLL40.SDI
IoInMux.O PLL40_2.BYPASS
IoInMux.O PLL40_2.DYNAMICDELAY[0]
IoInMux.O PLL40_2.DYNAMICDELAY[1]
IoInMux.O PLL40_2.DYNAMICDELAY[2]
IoInMux.O PLL40_2.DYNAMICDELAY[3]
IoInMux.O PLL40_2.DYNAMICDELAY[4]
IoInMux.O PLL40_2.DYNAMICDELAY[5]
IoInMux.O PLL40_2.DYNAMICDELAY[6]
IoInMux.O PLL40_2.DYNAMICDELAY[7]
IoInMux.O PLL40_2.EXTFEEDBACK
IoInMux.O PLL40_2.LATCHINPUTVALUE
IoInMux.O PLL40_2.RESETB
IoInMux.O PLL40_2.SCLK
IoInMux.O PLL40_2.SDI
IoInMux.O PLL40_2F.BYPASS
IoInMux.O PLL40_2F.DYNAMICDELAY[0]
IoInMux.O PLL40_2F.DYNAMICDELAY[1]
IoInMux.O PLL40_2F.DYNAMICDELAY[2]
IoInMux.O PLL40_2F.DYNAMICDELAY[3]
IoInMux.O PLL40_2F.DYNAMICDELAY[4]
IoInMux.O PLL40_2F.DYNAMICDELAY[5]
IoInMux.O PLL40_2F.DYNAMICDELAY[6]
IoInMux.O PLL40_2F.DYNAMICDELAY[7]
IoInMux.O PLL40_2F.EXTFEEDBACK
IoInMux.O PLL40_2F.LATCHINPUTVALUE
IoInMux.O PLL40_2F.RESETB
IoInMux.O PLL40_2F.SCLK
IoInMux.O PLL40_2F.SDI
IoInMux.O PRE_IO.DOUT0
IoInMux.O PRE_IO.DOUT1
IoInMux.O PRE_IO.LATCHINPUTVALUE
IoInMux.O PRE_IO.OUTPUTENABLE
IoInMux.O SB_PLL40_2F_CORE.BYPASS
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6]
IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7]
IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK
IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE
IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK
IoInMux.O SB_PLL40_2F_CORE.RESETB
IoInMux.O SB_PLL40_2F_CORE.SCLK
IoInMux.O SB_PLL40_2F_CORE.SDI
IoInMux.O SB_PLL40_CORE.BYPASS
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6]
IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7]
IoInMux.O SB_PLL40_CORE.EXTFEEDBACK
IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE
IoInMux.O SB_PLL40_CORE.REFERENCECLK
IoInMux.O SB_PLL40_CORE.RESETB
IoInMux.O SB_PLL40_CORE.SCLK
IoInMux.O SB_PLL40_CORE.SDI
IoSpan4Mux.O IoSpan4Mux.I
IoSpan4Mux.O LocalMux.I
IoSpan4Mux.O Span4Mux_h.I
IoSpan4Mux.O Span4Mux_s0_h.I
IoSpan4Mux.O Span4Mux_s0_v.I
IoSpan4Mux.O Span4Mux_s1_h.I
IoSpan4Mux.O Span4Mux_s1_v.I
IoSpan4Mux.O Span4Mux_s2_h.I
IoSpan4Mux.O Span4Mux_s2_v.I
IoSpan4Mux.O Span4Mux_s3_h.I
IoSpan4Mux.O Span4Mux_s3_v.I
IoSpan4Mux.O Span4Mux_v.I
LocalMux.O CEMux.I
LocalMux.O ClkMux.I
LocalMux.O InMux.I
LocalMux.O IoInMux.I
LocalMux.O SRMux.I
LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin
LogicCell40.carryout InMux.I
LogicCell40.carryout LogicCell40.carryin
LogicCell40.lcout LocalMux.I
LogicCell40.lcout Odrv12.I
LogicCell40.lcout Odrv4.I
LogicCell40.ltout CascadeMux.I
Odrv12.O LocalMux.I
Odrv12.O Sp12to4.I
Odrv12.O Span12Mux_s0_h.I
Odrv12.O Span12Mux_s0_v.I
Odrv12.O Span12Mux_s10_h.I
Odrv12.O Span12Mux_s10_v.I
Odrv12.O Span12Mux_s11_h.I
Odrv12.O Span12Mux_s11_v.I
Odrv12.O Span12Mux_s1_h.I
Odrv12.O Span12Mux_s1_v.I
Odrv12.O Span12Mux_s2_h.I
Odrv12.O Span12Mux_s2_v.I
Odrv12.O Span12Mux_s3_h.I
Odrv12.O Span12Mux_s3_v.I
Odrv12.O Span12Mux_s4_h.I
Odrv12.O Span12Mux_s4_v.I
Odrv12.O Span12Mux_s5_h.I
Odrv12.O Span12Mux_s5_v.I
Odrv12.O Span12Mux_s6_h.I
Odrv12.O Span12Mux_s6_v.I
Odrv12.O Span12Mux_s7_h.I
Odrv12.O Span12Mux_s7_v.I
Odrv12.O Span12Mux_s8_h.I
Odrv12.O Span12Mux_s8_v.I
Odrv12.O Span12Mux_s9_h.I
Odrv12.O Span12Mux_s9_v.I
Odrv12.O Span12Mux_v.I
Odrv4.O IoSpan4Mux.I
Odrv4.O LocalMux.I
Odrv4.O Span4Mux_h.I
Odrv4.O Span4Mux_s0_h.I
Odrv4.O Span4Mux_s0_v.I
Odrv4.O Span4Mux_s1_h.I
Odrv4.O Span4Mux_s1_v.I
Odrv4.O Span4Mux_s2_h.I
Odrv4.O Span4Mux_s2_v.I
Odrv4.O Span4Mux_s3_h.I
Odrv4.O Span4Mux_s3_v.I
Odrv4.O Span4Mux_v.I
PLL40.LOCK LocalMux.I
PLL40.PLLOUTCORE Odrv12.I
PLL40.PLLOUTCORE Odrv4.I
PLL40.PLLOUTGLOBAL GlobalMux.I
PLL40.SDO LocalMux.I
PLL40_2.LOCK LocalMux.I
PLL40_2.PLLOUTCOREA Odrv4.I
PLL40_2.PLLOUTCOREB LocalMux.I
PLL40_2.PLLOUTCOREB Odrv12.I
PLL40_2.PLLOUTGLOBALA GlobalMux.I
PLL40_2.PLLOUTGLOBALB GlobalMux.I
PLL40_2.SDO LocalMux.I
PLL40_2F.LOCK LocalMux.I
PLL40_2F.PLLOUTCOREA LocalMux.I
PLL40_2F.PLLOUTCOREA Odrv12.I
PLL40_2F.PLLOUTCOREA Odrv4.I
PLL40_2F.PLLOUTCOREB Odrv4.I
PLL40_2F.PLLOUTGLOBALA GlobalMux.I
PLL40_2F.PLLOUTGLOBALB GlobalMux.I
PLL40_2F.SDO LocalMux.I
PRE_IO.DIN0 LocalMux.I
PRE_IO.DIN0 Odrv12.I
PRE_IO.DIN0 Odrv4.I
PRE_IO.DIN1 LocalMux.I
PRE_IO.DIN1 Odrv12.I
PRE_IO.DIN1 Odrv4.I
PRE_IO.PADOEN IO_PAD.OE
PRE_IO.PADOUT IO_PAD.DIN
PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
SB_PLL40_2F_CORE.LOCK LocalMux.I
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv4.I
SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I
SB_PLL40_2F_CORE.PLLOUTCOREB Odrv4.I
SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I
SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I
SB_PLL40_2F_CORE.SDO LocalMux.I
SB_PLL40_CORE.LOCK LocalMux.I
SB_PLL40_CORE.PLLOUTCORE Odrv12.I
SB_PLL40_CORE.PLLOUTCORE Odrv4.I
SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I
SB_PLL40_CORE.SDO LocalMux.I
SB_RAM40_4K.RDATA[0] LocalMux.I
SB_RAM40_4K.RDATA[0] Odrv12.I
SB_RAM40_4K.RDATA[0] Odrv4.I
SB_RAM40_4K.RDATA[10] LocalMux.I
SB_RAM40_4K.RDATA[10] Odrv12.I
SB_RAM40_4K.RDATA[10] Odrv4.I
SB_RAM40_4K.RDATA[11] LocalMux.I
SB_RAM40_4K.RDATA[11] Odrv12.I
SB_RAM40_4K.RDATA[11] Odrv4.I
SB_RAM40_4K.RDATA[12] LocalMux.I
SB_RAM40_4K.RDATA[12] Odrv12.I
SB_RAM40_4K.RDATA[12] Odrv4.I
SB_RAM40_4K.RDATA[13] LocalMux.I
SB_RAM40_4K.RDATA[13] Odrv12.I
SB_RAM40_4K.RDATA[13] Odrv4.I
SB_RAM40_4K.RDATA[14] LocalMux.I
SB_RAM40_4K.RDATA[14] Odrv12.I
SB_RAM40_4K.RDATA[14] Odrv4.I
SB_RAM40_4K.RDATA[15] LocalMux.I
SB_RAM40_4K.RDATA[15] Odrv12.I
SB_RAM40_4K.RDATA[15] Odrv4.I
SB_RAM40_4K.RDATA[1] LocalMux.I
SB_RAM40_4K.RDATA[1] Odrv12.I
SB_RAM40_4K.RDATA[1] Odrv4.I
SB_RAM40_4K.RDATA[2] LocalMux.I
SB_RAM40_4K.RDATA[2] Odrv12.I
SB_RAM40_4K.RDATA[2] Odrv4.I
SB_RAM40_4K.RDATA[3] LocalMux.I
SB_RAM40_4K.RDATA[3] Odrv12.I
SB_RAM40_4K.RDATA[3] Odrv4.I
SB_RAM40_4K.RDATA[4] LocalMux.I
SB_RAM40_4K.RDATA[4] Odrv12.I
SB_RAM40_4K.RDATA[4] Odrv4.I
SB_RAM40_4K.RDATA[5] LocalMux.I
SB_RAM40_4K.RDATA[5] Odrv12.I
SB_RAM40_4K.RDATA[5] Odrv4.I
SB_RAM40_4K.RDATA[6] LocalMux.I
SB_RAM40_4K.RDATA[6] Odrv12.I
SB_RAM40_4K.RDATA[6] Odrv4.I
SB_RAM40_4K.RDATA[7] LocalMux.I
SB_RAM40_4K.RDATA[7] Odrv12.I
SB_RAM40_4K.RDATA[7] Odrv4.I
SB_RAM40_4K.RDATA[8] LocalMux.I
SB_RAM40_4K.RDATA[8] Odrv12.I
SB_RAM40_4K.RDATA[8] Odrv4.I
SB_RAM40_4K.RDATA[9] LocalMux.I
SB_RAM40_4K.RDATA[9] Odrv12.I
SB_RAM40_4K.RDATA[9] Odrv4.I
SRMux.O LogicCell40.sr
SRMux.O SB_RAM40_4K.RE
SRMux.O SB_RAM40_4K.WE
Sp12to4.O IoSpan4Mux.I
Sp12to4.O LocalMux.I
Sp12to4.O Span4Mux_h.I
Sp12to4.O Span4Mux_s0_h.I
Sp12to4.O Span4Mux_s0_v.I
Sp12to4.O Span4Mux_s1_h.I
Sp12to4.O Span4Mux_s1_v.I
Sp12to4.O Span4Mux_s2_h.I
Sp12to4.O Span4Mux_s2_v.I
Sp12to4.O Span4Mux_s3_h.I
Sp12to4.O Span4Mux_s3_v.I
Sp12to4.O Span4Mux_v.I
Span12Mux_s0_h.O LocalMux.I
Span12Mux_s0_h.O Sp12to4.I
Span12Mux_s0_v.O LocalMux.I
Span12Mux_s10_h.O LocalMux.I
Span12Mux_s10_h.O Sp12to4.I
Span12Mux_s10_v.O LocalMux.I
Span12Mux_s10_v.O Sp12to4.I
Span12Mux_s11_h.O LocalMux.I
Span12Mux_s11_h.O Sp12to4.I
Span12Mux_s11_v.O LocalMux.I
Span12Mux_s11_v.O Sp12to4.I
Span12Mux_s1_h.O LocalMux.I
Span12Mux_s1_h.O Sp12to4.I
Span12Mux_s1_v.O LocalMux.I
Span12Mux_s1_v.O Sp12to4.I
Span12Mux_s2_h.O LocalMux.I
Span12Mux_s2_h.O Sp12to4.I
Span12Mux_s2_v.O LocalMux.I
Span12Mux_s2_v.O Sp12to4.I
Span12Mux_s3_h.O LocalMux.I
Span12Mux_s3_h.O Sp12to4.I
Span12Mux_s3_v.O LocalMux.I
Span12Mux_s3_v.O Sp12to4.I
Span12Mux_s3_v.O Span12Mux_v.I
Span12Mux_s4_h.O LocalMux.I
Span12Mux_s4_h.O Sp12to4.I
Span12Mux_s4_v.O LocalMux.I
Span12Mux_s4_v.O Sp12to4.I
Span12Mux_s5_h.O LocalMux.I
Span12Mux_s5_h.O Sp12to4.I
Span12Mux_s5_v.O LocalMux.I
Span12Mux_s5_v.O Sp12to4.I
Span12Mux_s6_h.O LocalMux.I
Span12Mux_s6_h.O Sp12to4.I
Span12Mux_s6_v.O LocalMux.I
Span12Mux_s6_v.O Sp12to4.I
Span12Mux_s7_h.O LocalMux.I
Span12Mux_s7_h.O Sp12to4.I
Span12Mux_s7_h.O Span12Mux_s10_v.I
Span12Mux_s7_h.O Span12Mux_v.I
Span12Mux_s7_v.O LocalMux.I
Span12Mux_s7_v.O Sp12to4.I
Span12Mux_s7_v.O Span12Mux_s8_v.I
Span12Mux_s8_h.O LocalMux.I
Span12Mux_s8_h.O Sp12to4.I
Span12Mux_s8_v.O LocalMux.I
Span12Mux_s8_v.O Sp12to4.I
Span12Mux_s8_v.O Span12Mux_s8_h.I
Span12Mux_s9_h.O LocalMux.I
Span12Mux_s9_h.O Sp12to4.I
Span12Mux_s9_v.O LocalMux.I
Span12Mux_s9_v.O Sp12to4.I
Span12Mux_s9_v.O Span12Mux_s6_v.I
Span12Mux_v.O LocalMux.I
Span12Mux_v.O Sp12to4.I
Span12Mux_v.O Span12Mux_s0_h.I
Span12Mux_v.O Span12Mux_s0_v.I
Span12Mux_v.O Span12Mux_s10_h.I
Span12Mux_v.O Span12Mux_s11_h.I
Span12Mux_v.O Span12Mux_s1_v.I
Span12Mux_v.O Span12Mux_s2_h.I
Span12Mux_v.O Span12Mux_s2_v.I
Span12Mux_v.O Span12Mux_s3_h.I
Span12Mux_v.O Span12Mux_s3_v.I
Span12Mux_v.O Span12Mux_s4_h.I
Span12Mux_v.O Span12Mux_s5_h.I
Span12Mux_v.O Span12Mux_s6_h.I
Span12Mux_v.O Span12Mux_s7_h.I
Span12Mux_v.O Span12Mux_s8_h.I
Span12Mux_v.O Span12Mux_s9_h.I
Span4Mux_h.O LocalMux.I
Span4Mux_h.O Span4Mux_h.I
Span4Mux_h.O Span4Mux_s0_h.I
Span4Mux_h.O Span4Mux_s0_v.I
Span4Mux_h.O Span4Mux_s1_h.I
Span4Mux_h.O Span4Mux_s1_v.I
Span4Mux_h.O Span4Mux_s2_h.I
Span4Mux_h.O Span4Mux_s2_v.I
Span4Mux_h.O Span4Mux_s3_h.I
Span4Mux_h.O Span4Mux_s3_v.I
Span4Mux_h.O Span4Mux_v.I
Span4Mux_s0_h.O IoSpan4Mux.I
Span4Mux_s0_h.O LocalMux.I
Span4Mux_s0_h.O Span4Mux_h.I
Span4Mux_s0_h.O Span4Mux_v.I
Span4Mux_s0_v.O IoSpan4Mux.I
Span4Mux_s0_v.O LocalMux.I
Span4Mux_s0_v.O Span4Mux_h.I
Span4Mux_s0_v.O Span4Mux_s1_h.I
Span4Mux_s0_v.O Span4Mux_s3_h.I
Span4Mux_s0_v.O Span4Mux_v.I
Span4Mux_s1_h.O IoSpan4Mux.I
Span4Mux_s1_h.O LocalMux.I
Span4Mux_s1_h.O Span4Mux_h.I
Span4Mux_s1_h.O Span4Mux_s0_v.I
Span4Mux_s1_h.O Span4Mux_s1_v.I
Span4Mux_s1_h.O Span4Mux_s2_v.I
Span4Mux_s1_h.O Span4Mux_s3_v.I
Span4Mux_s1_h.O Span4Mux_v.I
Span4Mux_s1_v.O IoSpan4Mux.I
Span4Mux_s1_v.O LocalMux.I
Span4Mux_s1_v.O Span4Mux_h.I
Span4Mux_s1_v.O Span4Mux_s3_h.I
Span4Mux_s1_v.O Span4Mux_v.I
Span4Mux_s2_h.O IoSpan4Mux.I
Span4Mux_s2_h.O LocalMux.I
Span4Mux_s2_h.O Span4Mux_h.I
Span4Mux_s2_h.O Span4Mux_s0_v.I
Span4Mux_s2_h.O Span4Mux_s1_v.I
Span4Mux_s2_h.O Span4Mux_s2_v.I
Span4Mux_s2_h.O Span4Mux_s3_v.I
Span4Mux_s2_h.O Span4Mux_v.I
Span4Mux_s2_v.O IoSpan4Mux.I
Span4Mux_s2_v.O LocalMux.I
Span4Mux_s2_v.O Span4Mux_h.I
Span4Mux_s2_v.O Span4Mux_s1_h.I
Span4Mux_s2_v.O Span4Mux_s2_h.I
Span4Mux_s2_v.O Span4Mux_s3_h.I
Span4Mux_s2_v.O Span4Mux_v.I
Span4Mux_s3_h.O IoSpan4Mux.I
Span4Mux_s3_h.O LocalMux.I
Span4Mux_s3_h.O Span4Mux_h.I
Span4Mux_s3_h.O Span4Mux_s1_v.I
Span4Mux_s3_h.O Span4Mux_s2_v.I
Span4Mux_s3_h.O Span4Mux_s3_v.I
Span4Mux_s3_h.O Span4Mux_v.I
Span4Mux_s3_v.O IoSpan4Mux.I
Span4Mux_s3_v.O LocalMux.I
Span4Mux_s3_v.O Span4Mux_h.I
Span4Mux_s3_v.O Span4Mux_v.I
Span4Mux_v.O LocalMux.I
Span4Mux_v.O Span4Mux_h.I
Span4Mux_v.O Span4Mux_s0_h.I
Span4Mux_v.O Span4Mux_s0_v.I
Span4Mux_v.O Span4Mux_s1_h.I
Span4Mux_v.O Span4Mux_s1_v.I
Span4Mux_v.O Span4Mux_s2_h.I
Span4Mux_v.O Span4Mux_s2_v.I
Span4Mux_v.O Span4Mux_s3_h.I
Span4Mux_v.O Span4Mux_s3_v.I
Span4Mux_v.O Span4Mux_v.I
VCC.Y IO_PAD.OE
VCC.Y PRE_IO.CLOCKENABLE
gio2CtrlBuf.O GlobalMux.I