mirror of https://github.com/YosysHQ/icestorm.git
Work on timing analysis of DSPs
This commit is contained in:
David Shah
parent
49dfe15d8c
commit
cd4352e0ce
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@ -710,12 +710,19 @@ const std::set<std::string> &get_inports(std::string cell_type)
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inports_map["INTERCONN"] = { "I" };
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}
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std::string dsp_prefix = "SB_MAC16";
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if(cell_type.substr(0, dsp_prefix.length()) == dsp_prefix)
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cell_type = "SB_MAC16";
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if (inports_map.count(cell_type) == 0) {
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fprintf(stderr, "Missing entry in inports_map for cell type %s!\n", cell_type.c_str());
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exit(1);
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}
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return inports_map.at(cell_type);
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}
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@ -1243,6 +1250,154 @@ std::string make_lc40(int x, int y, int z)
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return cell;
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}
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bool get_dsp_ip_cbit(std::tuple<int, int, std::string> cbit) {
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std::string name = "IpConfig." + std::get<2>(cbit);
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// DSP0 contains all CBITs, the same as any DSP/IP tile
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if(dsp0_tile_bits.count(name)) {
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auto bitpos = dsp0_tile_bits.at(name)[0];
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return config_bits[std::get<0>(cbit)][std::get<1>(cbit)][bitpos.first][bitpos.second];
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}
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return false;
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}
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std::string make_dsp_ip(int x, int y, std::string net, std::string &primnet)
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{
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std::tuple<int, int, std::string> ecnet(x, y, net);
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std::tuple<std::string, int, int, int> key("", -1, -1, -1);
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bool found = false;
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for(auto ec : extra_cells) {
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for(auto entry : ec.second) {
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if(entry.second == ecnet) {
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key = ec.first;
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primnet = entry.first;
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found = true;
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break;
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}
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}
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}
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if(!found) {
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fprintf(stderr, "Error: net (%d, %d, '%s') does not correspond to any IP\n", x, y, net.c_str());
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exit(1);
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}
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int cx, cy, cz;
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std::string ectype;
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std::tie(ectype, cx, cy, cz) = key;
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auto cell = stringf("%s_%d_%d_%d", ectype.c_str(), cx, cy, cz);
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if (netlist_cell_types.count(cell))
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return cell;
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if(ectype == "MAC16") {
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// Given the few actual unique timing possibilites, only look at a subset
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// of the CBITs to pick the closest cell type from a timing point of view
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std::string dsptype = "";
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bool mode_8x8 = get_dsp_ip_cbit(extra_cells[key].at("MODE_8x8"));
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// It seems no different between any pipeline mode, so pick pipelining based
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// on one of the bits
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bool pipeline = get_dsp_ip_cbit(extra_cells[key].at("A_REG"));
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int botout = (get_dsp_ip_cbit(extra_cells[key].at("BOTOUTPUT_SELECT_1")) << 1) | get_dsp_ip_cbit(extra_cells[key].at("BOTOUTPUT_SELECT_0"));
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int botlwrin = (get_dsp_ip_cbit(extra_cells[key].at("BOTADDSUB_LOWERINPUT_1")) << 1) | get_dsp_ip_cbit(extra_cells[key].at("BOTADDSUB_LOWERINPUT_0"));
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bool botuprin = get_dsp_ip_cbit(extra_cells[key].at("BOTADDSUB_UPPERINPUT"));
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int topcarry = (get_dsp_ip_cbit(extra_cells[key].at("TOPADDSUB_CARRYSELECT_1")) << 1) | get_dsp_ip_cbit(extra_cells[key].at("TOPADDSUB_CARRYSELECT_0"));
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// Worst case default
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std::string basename = "SB_MAC16_MUL_U_16X16";
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// Note: signedness is ignored as it seems to have no effect
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if(mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 2)) {
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basename = "SB_MAC16_MUL_U_8X8";
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} else if (!mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 3)) {
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basename = "SB_MAC16_MUL_U_16X16";
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} else if (mode_8x8 && !botuprin && (botlwrin == 1) && (botout == 1)) {
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basename = "SB_MAC16_MAC_U_8X8";
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} else if (!mode_8x8 && !botuprin && (botlwrin == 2) && (botout == 1)) {
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basename = "SB_MAC16_MAC_U_16X16";
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} else if (mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 1) && (topcarry == 0)) {
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basename = "SB_MAC16_ACC_U_16P16";
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} else if (mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 1) && (topcarry == 2)) {
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basename = "SB_MAC16_ACC_U_32P32";
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} else if (mode_8x8 && botuprin && (botlwrin == 0) && (topcarry == 0)) {
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basename = "SB_MAC16_ADS_U_16P16";
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} else if (mode_8x8 && botuprin && (botlwrin == 0) && (topcarry == 2)) {
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basename = "SB_MAC16_ADS_U_32P32";
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} else if (mode_8x8 && botuprin && (botlwrin == 1)) {
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basename = "SB_MAC16_MAS_U_8X8";
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} else if (!mode_8x8 && botuprin && (botlwrin == 2)) {
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basename = "SB_MAC16_MAS_U_16X16";
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} else {
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fprintf(stderr, "Warning: detected unknown/unsupported DSP config, defaulting to 16x16 MUL.\n");
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}
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dsptype = basename + (pipeline ? "_ALL_PIPELINE" : "_BYPASS");
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netlist_cell_types[cell] = dsptype;
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for (int i = 0; i < 16; i++) {
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netlist_cell_ports[cell][stringf("C[%d]", i)] = "gnd";
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netlist_cell_ports[cell][stringf("A[%d]", i)] = "gnd";
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netlist_cell_ports[cell][stringf("B[%d]", i)] = "gnd";
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netlist_cell_ports[cell][stringf("D[%d]", i)] = "gnd";
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}
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netlist_cell_ports[cell]["CLK"] = "";
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netlist_cell_ports[cell]["CE"] = "";
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netlist_cell_ports[cell]["AHOLD"] = "gnd";
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netlist_cell_ports[cell]["BHOLD"] = "gnd";
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netlist_cell_ports[cell]["CHOLD"] = "gnd";
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netlist_cell_ports[cell]["DHOLD"] = "gnd";
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netlist_cell_ports[cell]["IRSTTOP"] = "";
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netlist_cell_ports[cell]["IRSTBOT"] = "";
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netlist_cell_ports[cell]["ORSTTOP"] = "";
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netlist_cell_ports[cell]["ORSTBOT"] = "";
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netlist_cell_ports[cell]["OLOADTOP"] = "gnd";
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netlist_cell_ports[cell]["OLOADBOT"] = "gnd";
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netlist_cell_ports[cell]["ADDSUBTOP"] = "gnd";
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netlist_cell_ports[cell]["ADDSUBBOT"] = "gnd";
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netlist_cell_ports[cell]["OHOLDTOP"] = "gnd";
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netlist_cell_ports[cell]["OHOLDBOT"] = "gnd";
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netlist_cell_ports[cell]["CI"] = "gnd";
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netlist_cell_ports[cell]["ACCUMCI"] = "";
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netlist_cell_ports[cell]["SIGNEXTIN"] = "";
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for (int i = 0; i < 32; i++) {
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netlist_cell_ports[cell][stringf("O[%d]", i)] = "";
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}
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netlist_cell_ports[cell]["ACCUMCO"] = "";
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netlist_cell_ports[cell]["SIGNEXTOUT"] = "";
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return cell;
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} else if(ectype == "SPRAM256KA") {
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netlist_cell_types[cell] = "SB_SPRAM256KA";
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for (int i = 0; i < 14; i++) {
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netlist_cell_ports[cell][stringf("ADDRESS[%d]", i)] = "gnd";
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}
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for (int i = 0; i < 16; i++) {
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netlist_cell_ports[cell][stringf("DATAIN[%d]", i)] = "gnd";
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netlist_cell_ports[cell][stringf("DATAOUT[%d]", i)] = "";
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}
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netlist_cell_ports[cell]["MASKWREN[3]"] = "gnd";
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netlist_cell_ports[cell]["MASKWREN[2]"] = "gnd";
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netlist_cell_ports[cell]["MASKWREN[1]"] = "gnd";
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netlist_cell_ports[cell]["MASKWREN[0]"] = "gnd";
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netlist_cell_ports[cell]["WREN"] = "gnd";
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netlist_cell_ports[cell]["CHIPSELECT"] = "gnd";
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netlist_cell_ports[cell]["CLOCK"] = "";
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netlist_cell_ports[cell]["STANDBY"] = "gnd";
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netlist_cell_ports[cell]["SLEEP"] = "gnd";
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netlist_cell_ports[cell]["POWEROFF"] = "gnd";
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return cell;
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} else {
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netlist_cell_types[cell] = "SB_" + ectype;
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fprintf(stderr, "Warning: timing analysis not supported for cell type %s\n", ectype.c_str());
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return cell;
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}
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}
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std::string make_ram(int x, int y)
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{
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auto cell = stringf("ram_%d_%d", x, y);
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@ -1377,17 +1532,28 @@ void make_seg_cell(int net, const net_segment_t &seg)
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}
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if (sscanf(seg.name.c_str(), "lutff_%d/in_%d", &a, &b) == 2) {
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auto cell = make_lc40(seg.x, seg.y, a);
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if (b == 2) {
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// Lattice tools always put a CascadeMux on in2
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netlist_cell_ports[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
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//"logic" wires at the side of the device are actually IP or DSP
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if(device_type == "up5k" && ((seg.x == 0) || (seg.x == config_tile_type.size() - 1))) {
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std::string primnet;
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auto cell = make_dsp_ip(seg.x, seg.y, seg.name, primnet);
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if(cell != "") {
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make_inmux(seg.x, seg.y, net);
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}
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return;
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} else {
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netlist_cell_ports[cell][stringf("in%d", b)] = net_name(net);
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auto cell = make_lc40(seg.x, seg.y, a);
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if (b == 2) {
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// Lattice tools always put a CascadeMux on in2
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netlist_cell_ports[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
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} else {
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netlist_cell_ports[cell][stringf("in%d", b)] = net_name(net);
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}
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make_inmux(seg.x, seg.y, net);
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}
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make_inmux(seg.x, seg.y, net);
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return;
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}
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if (sscanf(seg.name.c_str(), "lutff_%d/ou%c", &a, &c) == 2 && c == 't')
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{
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for (int dst_net : net_buffers.at(seg.net))
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@ -1406,6 +1572,28 @@ void make_seg_cell(int net, const net_segment_t &seg)
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return;
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}
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if (sscanf(seg.name.c_str(), "slf_op_%d", &a) == 1)
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{
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std::string primnet;
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auto cell = make_dsp_ip(seg.x, seg.y, seg.name, primnet);
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if(cell != "") {
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netlist_cell_ports[cell][primnet] = net_name(net);
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make_odrv(seg.x, seg.y, net);
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}
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return;
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}
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if (sscanf(seg.name.c_str(), "mult/O_%d", &a) == 1)
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{
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std::string primnet;
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auto cell = make_dsp_ip(seg.x, seg.y, seg.name, primnet);
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if(cell != "") {
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netlist_cell_ports[cell][primnet] = net_name(net);
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make_odrv(seg.x, seg.y, net);
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}
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return;
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}
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if (sscanf(seg.name.c_str(), "lutff_%d/cou%c", &a, &c) == 2 && c == 't')
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{
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auto cell = make_lc40(seg.x, seg.y, a);
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