mirror of https://github.com/YosysHQ/icestorm.git
Fix some of docs table layouts
This commit is contained in:
Miodrag Milanovic
parent
789a46da5e
commit
afb459ae2a
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@ -26,11 +26,17 @@ The following commands are known:
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| Opcode | Description |
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+===================================+===================================+
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| 0 | payload=1: Write CRAM Data |
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| +-----------------------------------+
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| | payload=2: Read BRAM Data |
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| +-----------------------------------+
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| | payload=3: Write BRAM Data |
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| +-----------------------------------+
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| | payload=4: Read BRAM Data |
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| +-----------------------------------+
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| | payload=5: Reset CRC |
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| +-----------------------------------+
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| | payload=6: Wakeup |
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| +-----------------------------------+
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| | payload=8: Reboot |
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+-----------------------------------+-----------------------------------+
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| 1 | Set bank number |
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@ -41,8 +47,11 @@ The following commands are known:
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+-----------------------------------+-----------------------------------+
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| 5 | Set internal oscillator frequency |
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| | range |
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| +-----------------------------------+
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| | payload=0: low |
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| +-----------------------------------+
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| | payload=1: medium |
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| +-----------------------------------+
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| | payload=2: high |
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+-----------------------------------+-----------------------------------+
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| 6 | Set bank width (16-bits, MSB |
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@ -55,7 +64,9 @@ The following commands are known:
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| | first) |
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+-----------------------------------+-----------------------------------+
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| 9 | payload=0: Disable warm boot |
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| +-----------------------------------+
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| | payload=16: Enable cold boot |
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| +-----------------------------------+
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| | payload=32: Enable warm boot |
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+-----------------------------------+-----------------------------------+
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@ -327,11 +327,17 @@ configured as follows (bits listed from LSB to MSB):
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| | | Parameter |
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+=======================+=======================+=======================+
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| 0 3 | PLLCONFIG_5 | Select PLL Type: |
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| | +-----------------------+
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| | | 000 = DISABLED |
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| | +-----------------------+
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| | | 010 = SB_PLL40_PAD |
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| | +-----------------------+
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| | | 100 = SB_PLL40_2_PAD |
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| | +-----------------------+
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| | | 110 = SB_PLL40_2F_PAD |
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| | +-----------------------+
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| | | 011 = SB_PLL40_CORE |
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| | +-----------------------+
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| | | 111 = |
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| | | SB_PLL40_2F_CORE |
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+-----------------------+-----------------------+-----------------------+
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@ -340,10 +346,14 @@ configured as follows (bits listed from LSB to MSB):
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| 0 5 | PLLCONFIG_3 | |
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+-----------------------+-----------------------+-----------------------+
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| 0 5 | PLLCONFIG_5 | FEEDBACK_PATH |
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| | +-----------------------+
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| | | 000 = "DELAY" |
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| | +-----------------------+
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| | | 001 = "SIMPLE" |
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| | +-----------------------+
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| | | 010 = |
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| | | "PHASE_AND_DELAY" |
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| | +-----------------------+
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| | | 110 = "EXTERNAL" |
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+-----------------------+-----------------------+-----------------------+
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| 0 2 | PLLCONFIG_9 | |
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@ -352,27 +362,39 @@ configured as follows (bits listed from LSB to MSB):
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+-----------------------+-----------------------+-----------------------+
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| 0 4 | PLLCONFIG_4 | DELAY_ADJ |
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| | | USTMENT_MODE_FEEDBACK |
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| | +-----------------------+
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| | | 0 = "FIXED" |
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| | +-----------------------+
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| | | 1 = "DYNAMIC" |
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+-----------------------+-----------------------+-----------------------+
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| 0 4 | PLLCONFIG_9 | DELAY_ADJ |
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| | | USTMENT_MODE_RELATIVE |
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| | +-----------------------+
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| | | 0 = "FIXED" |
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| | +-----------------------+
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| | | 1 = "DYNAMIC" |
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+-----------------------+-----------------------+-----------------------+
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| 0 3 | PLLCONFIG_6 | PLLOUT_SELECT |
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| | | PLLOUT_SELECT_PORTA |
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| | +-----------------------+
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| | | 00 = "GENCLK" |
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| | +-----------------------+
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| | | 01 = "GENCLK_HALF" |
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| | +-----------------------+
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| | | 10 = "SHIFTREG_90deg" |
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| | +-----------------------+
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| | | 11 = "SHIFTREG_0deg" |
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+-----------------------+-----------------------+-----------------------+
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| 0 3 | PLLCONFIG_7 | |
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+-----------------------+-----------------------+-----------------------+
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| 0 3 | PLLCONFIG_2 | PLLOUT_SELECT_PORTB |
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| | +-----------------------+
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| | | 00 = "GENCLK" |
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| | +-----------------------+
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| | | 01 = "GENCLK_HALF" |
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| | +-----------------------+
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| | | 10 = "SHIFTREG_90deg" |
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| | +-----------------------+
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| | | 11 = "SHIFTREG_0deg" |
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+-----------------------+-----------------------+-----------------------+
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| 0 3 | PLLCONFIG_3 | |
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@ -32,98 +32,64 @@ of signals and configuration bits is documented below.
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| **Signal Assignments**
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+----------+----------+----------+----------+----------+----------+
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| SB_MAC16 | DSP0 | DSP1 | DSP2 | DSP3 | IPCON4 |
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| port | | | | | |
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+==========+==========+==========+==========+==========+==========+
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| CLK | -- | -- | lutff_gl | -- | -- |
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| | | | obal/clk | | |
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+----------+----------+----------+----------+----------+----------+
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| CE | -- | -- | lutff_gl | -- | -- |
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| | | | obal/cen | | |
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+----------+----------+----------+----------+----------+----------+
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| C[7:0] | -- | -- | -- | l | -- |
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| | | | | utff\_[7 | |
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| | | | | :0]/in_3 | |
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+----------+----------+----------+----------+----------+----------+
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| C[15:8] | -- | -- | -- | l | -- |
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| | | | | utff\_[7 | |
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| | | | | :0]/in_1 | |
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+----------+----------+----------+----------+----------+----------+
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| A[7:0] | -- | -- | l | -- | -- |
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| | | | utff\_[7 | | |
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| | | | :0]/in_3 | | |
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+----------+----------+----------+----------+----------+----------+
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| A[15:8] | -- | -- | l | -- | -- |
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| | | | utff\_[7 | | |
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| | | | :0]/in_1 | | |
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+----------+----------+----------+----------+----------+----------+
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| B[7:0] | -- | l | -- | -- | -- |
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| | | utff\_[7 | | | |
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| | | :0]/in_3 | | | |
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+----------+----------+----------+----------+----------+----------+
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| B[15:8] | -- | l | -- | -- | -- |
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| | | utff\_[7 | | | |
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| | | :0]/in_1 | | | |
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+----------+----------+----------+----------+----------+----------+
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| D[7:0] | l | -- | -- | -- | -- |
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| | utff\_[7 | | | | |
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| | :0]/in_3 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| D[15:8] | l | -- | -- | -- | -- |
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| | utff\_[7 | | | | |
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| | :0]/in_1 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| IRSTTOP | -- | lutff_gl | -- | -- | -- |
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| | | obal/s_r | | | |
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+----------+----------+----------+----------+----------+----------+
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| IRSTBOT | lutff_gl | -- | -- | -- | -- |
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| | obal/s_r | | | | |
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+----------+----------+----------+----------+----------+----------+
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| ORSTTOP | -- | -- | -- | lutff_gl | -- |
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| | | | | obal/s_r | |
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+----------+----------+----------+----------+----------+----------+
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| ORSTBOT | -- | -- | lutff_gl | -- | -- |
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| | | | obal/s_r | | |
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+----------+----------+----------+----------+----------+----------+
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| AHOLD | -- | -- | lutf | -- | -- |
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| | | | f_0/in_0 | | |
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+----------+----------+----------+----------+----------+----------+
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| BHOLD | -- | lutf | -- | -- | -- |
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| | | f_0/in_0 | | | |
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+----------+----------+----------+----------+----------+----------+
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| CHOLD | -- | -- | -- | lutf | -- |
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| | | | | f_0/in_0 | |
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+----------+----------+----------+----------+----------+----------+
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| DHOLD | lutf | -- | -- | -- | -- |
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| | f_0/in_0 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| OHOLDTOP | -- | -- | -- | lutf | -- |
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| | | | | f_1/in_0 | |
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+----------+----------+----------+----------+----------+----------+
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| OHOLDBOT | lutf | -- | -- | -- | -- |
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| | f_1/in_0 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| A | -- | -- | -- | lutf | -- |
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| DDSUBTOP | | | | f_3/in_0 | |
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+----------+----------+----------+----------+----------+----------+
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| A | lutf | -- | -- | -- | -- |
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| DDSUBBOT | f_3/in_0 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| OLOADTOP | -- | -- | -- | lutf | -- |
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| | | | | f_2/in_0 | |
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+----------+----------+----------+----------+----------+----------+
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| OLOADBOT | lutf | -- | -- | -- | -- |
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| | f_2/in_0 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| CI | lutf | -- | -- | -- | -- |
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| | f_4/in_0 | | | | |
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+----------+----------+----------+----------+----------+----------+
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| O[31:0] | mult/ | mult/O | mult/O\ | mult/O\ | -- |
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| | O\_[7:0] | \_[15:8] | _[23:16] | _[31:24] | |
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+----------+----------+----------+----------+----------+----------+
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+==========+=====================+=====================+=====================+=====================+=====================+
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| CLK | -- | -- | lutff_global/clk | -- | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| CE | -- | -- | lutff_global/cen | -- | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| C[7:0] | -- | -- | -- | lutff\_[7:0]/in_3 | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| C[15:8] | -- | -- | -- | lutff\_[7:0]/in_1 | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| A[7:0] | -- | -- | lutff\_[7:0]/in_3 | -- | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| A[15:8] | -- | -- | lutff\_[7:0]/in_1 | -- | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| B[7:0] | -- | lutff\_[7:0]/in_3 | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| B[15:8] | -- | lutff\_[7:0]/in_1 | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| D[7:0] | lutff\_[7:0]/in_3 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| D[15:8] | lutff\_[7:0]/in_1 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| IRSTTOP | -- | lutff_global/s_r | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| IRSTBOT | lutff_global/s_r | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| ORSTTOP | -- | -- | -- | lutff_global/s_r | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| ORSTBOT | -- | -- | lutff_global/s_r | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| AHOLD | -- | -- | lutff_0/in_0 | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| BHOLD | -- | lutff_0/in_0 | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| CHOLD | -- | -- | -- | lutff_0/in_0 | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| DHOLD | lutff_0/in_0 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| OHOLDTOP | -- | -- | -- | lutff_1/in_0 | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| OHOLDBOT | lutff_1/in_0 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| A | -- | -- | -- | lutff_3/in_0 | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| A | lutff_3/in_0 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| OLOADTOP | -- | -- | -- | lutff_2/in_0 | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| OLOADBOT | lutff_2/in_0 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| CI | lutff_4/in_0 | | | | |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| O[31:0] | mult/O\_[7:0] | mult/O\_[15:8] | mult/O\_[23:16] | mult/O\_[31:24] | -- |
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| CO | -- | -- | -- | -- | slf_op_0 |
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+----------+----------+----------+----------+----------+----------+
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+----------+---------------------+---------------------+---------------------+---------------------+---------------------+
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| **Configuration Bits**
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@ -141,58 +107,52 @@ bits are then located in IPConnect tile (0, 19) CBIT[6:3].
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The full list of configuration bits, including the changes for the DSP
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at (0, 15) are described in the table below.
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| Parameter | Normal Position | DSP (0, 15) |
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| | | Changes |
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+=======================+=======================+=======================+
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+============================+=======================+=======================+
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| C_REG | DSP0.CBIT_0 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| A_REG | DSP0.CBIT_1 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| B_REG | DSP0.CBIT_2 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| D_REG | DSP0.CBIT_3 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| TOP_8x8_MULT_REG | DSP0.CBIT_4 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| BOT_8x8_MULT_REG | DSP0.CBIT_5 | |
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+-----------------------+-----------------------+-----------------------+
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| PIP | DSP0.CBIT_6 | |
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| ELINE_16x16_MULT_REG1 | | |
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+-----------------------+-----------------------+-----------------------+
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| PIP | DSP0.CBIT_7 | |
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| ELINE_16x16_MULT_REG2 | | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| PIPELINE_16x16_MULT_REG1 | DSP0.CBIT_6 | |
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+----------------------------+-----------------------+-----------------------+
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| PIPELINE_16x16_MULT_REG2 | DSP0.CBIT_7 | |
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+----------------------------+-----------------------+-----------------------+
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| TOPOUTPUT_SELECT[0] | DSP1.CBIT_0 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| TOPOUTPUT_SELECT[1] | DSP1.CBIT_1 | (0, 19).CBIT_3 |
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+-----------------------+-----------------------+-----------------------+
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| TOPA | DSP1.CBIT\_[3:2] | (0, 19).CBIT\_[5:4] |
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| DDSUB_LOWERINPUT[1:0] | | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| TOPADDSUB_LOWERINPUT[1:0] | DSP1.CBIT\_[3:2] | (0, 19).CBIT\_[5:4] |
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+----------------------------+-----------------------+-----------------------+
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| TOPADDSUB_UPPERINUT | DSP1.CBIT_4 | (0, 19).CBIT_6 |
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+-----------------------+-----------------------+-----------------------+
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| TOPAD | DSP1.CBIT\_[6:5] | |
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| DSUB_CARRYSELECT[1:0] | | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| TOPADDSUB_CARRYSELECT[1:0] | DSP1.CBIT\_[6:5] | |
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+----------------------------+-----------------------+-----------------------+
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| BOTOUTPUT_SELECT[0] | DSP1.CBIT_7 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| BOTOUTPUT_SELECT[1] | DSP2.CBIT_0 | |
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+-----------------------+-----------------------+-----------------------+
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| BOTA | DSP2.CBIT\_[2:1] | |
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| DDSUB_LOWERINPUT[1:0] | | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| BOTADDSUB_LOWERINPUT[1:0] | DSP2.CBIT\_[2:1] | |
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+----------------------------+-----------------------+-----------------------+
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| BOTADDSUB_UPPERINPUT | DSP2.CBIT_3 | |
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+-----------------------+-----------------------+-----------------------+
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| BOTAD | DSP2.CBIT\_[5:4] | |
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| DSUB_CARRYSELECT[1:0] | | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| BOTADDSUB_CARRYSELECT[1:0] | DSP2.CBIT\_[5:4] | |
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+----------------------------+-----------------------+-----------------------+
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| MODE_8x8 | DSP2.CBIT_6 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| A_SIGNED | DSP2.CBIT_7 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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| B_SIGNED | DSP3.CBIT_0 | |
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+-----------------------+-----------------------+-----------------------+
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+----------------------------+-----------------------+-----------------------+
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Lattice document a limited number of supported configurations in the ICE
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Technology Library document, and Lattice's EDIF parser will reject
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