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Fix some of docs table layouts

This commit is contained in:
Miodrag Milanovic 2024-12-11 13:06:06 +01:00
parent 789a46da5e
commit afb459ae2a
3 changed files with 137 additions and 144 deletions
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11
docs/source/format.rst
View File

@ -26,11 +26,17 @@ The following commands are known:
| Opcode | Description | | Opcode | Description |
+===================================+===================================+ +===================================+===================================+
| 0 | payload=1: Write CRAM Data | | 0 | payload=1: Write CRAM Data |
| +-----------------------------------+
| | payload=2: Read BRAM Data | | | payload=2: Read BRAM Data |
| +-----------------------------------+
| | payload=3: Write BRAM Data | | | payload=3: Write BRAM Data |
| +-----------------------------------+
| | payload=4: Read BRAM Data | | | payload=4: Read BRAM Data |
| +-----------------------------------+
| | payload=5: Reset CRC | | | payload=5: Reset CRC |
| +-----------------------------------+
| | payload=6: Wakeup | | | payload=6: Wakeup |
| +-----------------------------------+
| | payload=8: Reboot | | | payload=8: Reboot |
+-----------------------------------+-----------------------------------+ +-----------------------------------+-----------------------------------+
| 1 | Set bank number | | 1 | Set bank number |
@ -41,8 +47,11 @@ The following commands are known:
+-----------------------------------+-----------------------------------+ +-----------------------------------+-----------------------------------+
| 5 | Set internal oscillator frequency | | 5 | Set internal oscillator frequency |
| | range | | | range |
| +-----------------------------------+
| | payload=0: low | | | payload=0: low |
| +-----------------------------------+
| | payload=1: medium | | | payload=1: medium |
| +-----------------------------------+
| | payload=2: high | | | payload=2: high |
+-----------------------------------+-----------------------------------+ +-----------------------------------+-----------------------------------+
| 6 | Set bank width (16-bits, MSB | | 6 | Set bank width (16-bits, MSB |
@ -55,7 +64,9 @@ The following commands are known:
| | first) | | | first) |
+-----------------------------------+-----------------------------------+ +-----------------------------------+-----------------------------------+
| 9 | payload=0: Disable warm boot | | 9 | payload=0: Disable warm boot |
| +-----------------------------------+
| | payload=16: Enable cold boot | | | payload=16: Enable cold boot |
| +-----------------------------------+
| | payload=32: Enable warm boot | | | payload=32: Enable warm boot |
+-----------------------------------+-----------------------------------+ +-----------------------------------+-----------------------------------+

22
docs/source/io_tile.rst
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@ -327,11 +327,17 @@ configured as follows (bits listed from LSB to MSB):
| | | Parameter | | | | Parameter |
+=======================+=======================+=======================+ +=======================+=======================+=======================+
| 0 3 | PLLCONFIG_5 | Select PLL Type: | | 0 3 | PLLCONFIG_5 | Select PLL Type: |
| | +-----------------------+
| | | 000 = DISABLED | | | | 000 = DISABLED |
| | +-----------------------+
| | | 010 = SB_PLL40_PAD | | | | 010 = SB_PLL40_PAD |
| | +-----------------------+
| | | 100 = SB_PLL40_2_PAD | | | | 100 = SB_PLL40_2_PAD |
| | +-----------------------+
| | | 110 = SB_PLL40_2F_PAD | | | | 110 = SB_PLL40_2F_PAD |
| | +-----------------------+
| | | 011 = SB_PLL40_CORE | | | | 011 = SB_PLL40_CORE |
| | +-----------------------+
| | | 111 = | | | | 111 = |
| | | SB_PLL40_2F_CORE | | | | SB_PLL40_2F_CORE |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
@ -340,10 +346,14 @@ configured as follows (bits listed from LSB to MSB):
| 0 5 | PLLCONFIG_3 | | | 0 5 | PLLCONFIG_3 | |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 5 | PLLCONFIG_5 | FEEDBACK_PATH | | 0 5 | PLLCONFIG_5 | FEEDBACK_PATH |
| | +-----------------------+
| | | 000 = "DELAY" | | | | 000 = "DELAY" |
| | +-----------------------+
| | | 001 = "SIMPLE" | | | | 001 = "SIMPLE" |
| | +-----------------------+
| | | 010 = | | | | 010 = |
| | | "PHASE_AND_DELAY" | | | | "PHASE_AND_DELAY" |
| | +-----------------------+
| | | 110 = "EXTERNAL" | | | | 110 = "EXTERNAL" |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 2 | PLLCONFIG_9 | | | 0 2 | PLLCONFIG_9 | |
@ -352,27 +362,39 @@ configured as follows (bits listed from LSB to MSB):
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 4 | PLLCONFIG_4 | DELAY_ADJ | | 0 4 | PLLCONFIG_4 | DELAY_ADJ |
| | | USTMENT_MODE_FEEDBACK | | | | USTMENT_MODE_FEEDBACK |
| | +-----------------------+
| | | 0 = "FIXED" | | | | 0 = "FIXED" |
| | +-----------------------+
| | | 1 = "DYNAMIC" | | | | 1 = "DYNAMIC" |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 4 | PLLCONFIG_9 | DELAY_ADJ | | 0 4 | PLLCONFIG_9 | DELAY_ADJ |
| | | USTMENT_MODE_RELATIVE | | | | USTMENT_MODE_RELATIVE |
| | +-----------------------+
| | | 0 = "FIXED" | | | | 0 = "FIXED" |
| | +-----------------------+
| | | 1 = "DYNAMIC" | | | | 1 = "DYNAMIC" |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_6 | PLLOUT_SELECT | | 0 3 | PLLCONFIG_6 | PLLOUT_SELECT |
| | | PLLOUT_SELECT_PORTA | | | | PLLOUT_SELECT_PORTA |
| | +-----------------------+
| | | 00 = "GENCLK" | | | | 00 = "GENCLK" |
| | +-----------------------+
| | | 01 = "GENCLK_HALF" | | | | 01 = "GENCLK_HALF" |
| | +-----------------------+
| | | 10 = "SHIFTREG_90deg" | | | | 10 = "SHIFTREG_90deg" |
| | +-----------------------+
| | | 11 = "SHIFTREG_0deg" | | | | 11 = "SHIFTREG_0deg" |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_7 | | | 0 3 | PLLCONFIG_7 | |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_2 | PLLOUT_SELECT_PORTB | | 0 3 | PLLCONFIG_2 | PLLOUT_SELECT_PORTB |
| | +-----------------------+
| | | 00 = "GENCLK" | | | | 00 = "GENCLK" |
| | +-----------------------+
| | | 01 = "GENCLK_HALF" | | | | 01 = "GENCLK_HALF" |
| | +-----------------------+
| | | 10 = "SHIFTREG_90deg" | | | | 10 = "SHIFTREG_90deg" |
| | +-----------------------+
| | | 11 = "SHIFTREG_0deg" | | | | 11 = "SHIFTREG_0deg" |
+-----------------------+-----------------------+-----------------------+ +-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_3 | | | 0 3 | PLLCONFIG_3 | |

248
docs/source/ultraplus.rst
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@ -32,98 +32,64 @@ of signals and configuration bits is documented below.
| **Signal Assignments** | **Signal Assignments**
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| SB_MAC16 | DSP0 | DSP1 | DSP2 | DSP3 | IPCON4 | | SB_MAC16 | DSP0 | DSP1 | DSP2 | DSP3 | IPCON4 |
| port | | | | | | | port | | | | | |
+==========+==========+==========+==========+==========+==========+ +==========+=====================+=====================+=====================+=====================+=====================+
| CLK | -- | -- | lutff_gl | -- | -- | | CLK | -- | -- | lutff_global/clk | -- | -- |
| | | | obal/clk | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+----------+----------+----------+----------+----------+----------+ | CE | -- | -- | lutff_global/cen | -- | -- |
| CE | -- | -- | lutff_gl | -- | -- | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | | obal/cen | | | | C[7:0] | -- | -- | -- | lutff\_[7:0]/in_3 | -- |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| C[7:0] | -- | -- | -- | l | -- | | C[15:8] | -- | -- | -- | lutff\_[7:0]/in_1 | -- |
| | | | | utff\_[7 | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | | | :0]/in_3 | | | A[7:0] | -- | -- | lutff\_[7:0]/in_3 | -- | -- |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| C[15:8] | -- | -- | -- | l | -- | | A[15:8] | -- | -- | lutff\_[7:0]/in_1 | -- | -- |
| | | | | utff\_[7 | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | | | :0]/in_1 | | | B[7:0] | -- | lutff\_[7:0]/in_3 | | | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| A[7:0] | -- | -- | l | -- | -- | | B[15:8] | -- | lutff\_[7:0]/in_1 | | | |
| | | | utff\_[7 | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | | :0]/in_3 | | | | D[7:0] | lutff\_[7:0]/in_3 | | | | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| A[15:8] | -- | -- | l | -- | -- | | D[15:8] | lutff\_[7:0]/in_1 | | | | |
| | | | utff\_[7 | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | | :0]/in_1 | | | | IRSTTOP | -- | lutff_global/s_r | | | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| B[7:0] | -- | l | -- | -- | -- | | IRSTBOT | lutff_global/s_r | | | | |
| | | utff\_[7 | | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | :0]/in_3 | | | | | ORSTTOP | -- | -- | -- | lutff_global/s_r | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| B[15:8] | -- | l | -- | -- | -- | | ORSTBOT | -- | -- | lutff_global/s_r | | |
| | | utff\_[7 | | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | :0]/in_1 | | | | | AHOLD | -- | -- | lutff_0/in_0 | | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| D[7:0] | l | -- | -- | -- | -- | | BHOLD | -- | lutff_0/in_0 | | | |
| | utff\_[7 | | | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | :0]/in_3 | | | | | | CHOLD | -- | -- | -- | lutff_0/in_0 | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| D[15:8] | l | -- | -- | -- | -- | | DHOLD | lutff_0/in_0 | | | | |
| | utff\_[7 | | | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | :0]/in_1 | | | | | | OHOLDTOP | -- | -- | -- | lutff_1/in_0 | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| IRSTTOP | -- | lutff_gl | -- | -- | -- | | OHOLDBOT | lutff_1/in_0 | | | | |
| | | obal/s_r | | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+----------+----------+----------+----------+----------+----------+ | A | -- | -- | -- | lutff_3/in_0 | |
| IRSTBOT | lutff_gl | -- | -- | -- | -- | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | obal/s_r | | | | | | A | lutff_3/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| ORSTTOP | -- | -- | -- | lutff_gl | -- | | OLOADTOP | -- | -- | -- | lutff_2/in_0 | |
| | | | | obal/s_r | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+----------+----------+----------+----------+----------+----------+ | OLOADBOT | lutff_2/in_0 | | | | |
| ORSTBOT | -- | -- | lutff_gl | -- | -- | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | | obal/s_r | | | | CI | lutff_4/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+ +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| AHOLD | -- | -- | lutf | -- | -- | | O[31:0] | mult/O\_[7:0] | mult/O\_[15:8] | mult/O\_[23:16] | mult/O\_[31:24] | -- |
| | | | f_0/in_0 | | | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+----------+----------+----------+----------+----------+----------+ | CO | -- | -- | -- | -- | slf_op_0 |
| BHOLD | -- | lutf | -- | -- | -- | +----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| | | f_0/in_0 | | | |
+----------+----------+----------+----------+----------+----------+
| CHOLD | -- | -- | -- | lutf | -- |
| | | | | f_0/in_0 | |
+----------+----------+----------+----------+----------+----------+
| DHOLD | lutf | -- | -- | -- | -- |
| | f_0/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+
| OHOLDTOP | -- | -- | -- | lutf | -- |
| | | | | f_1/in_0 | |
+----------+----------+----------+----------+----------+----------+
| OHOLDBOT | lutf | -- | -- | -- | -- |
| | f_1/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+
| A | -- | -- | -- | lutf | -- |
| DDSUBTOP | | | | f_3/in_0 | |
+----------+----------+----------+----------+----------+----------+
| A | lutf | -- | -- | -- | -- |
| DDSUBBOT | f_3/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+
| OLOADTOP | -- | -- | -- | lutf | -- |
| | | | | f_2/in_0 | |
+----------+----------+----------+----------+----------+----------+
| OLOADBOT | lutf | -- | -- | -- | -- |
| | f_2/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+
| CI | lutf | -- | -- | -- | -- |
| | f_4/in_0 | | | | |
+----------+----------+----------+----------+----------+----------+
| O[31:0] | mult/ | mult/O | mult/O\ | mult/O\ | -- |
| | O\_[7:0] | \_[15:8] | _[23:16] | _[31:24] | |
+----------+----------+----------+----------+----------+----------+
| CO | -- | -- | -- | -- | slf_op_0 |
+----------+----------+----------+----------+----------+----------+
| **Configuration Bits** | **Configuration Bits**
@ -141,58 +107,52 @@ bits are then located in IPConnect tile (0, 19) CBIT[6:3].
The full list of configuration bits, including the changes for the DSP The full list of configuration bits, including the changes for the DSP
at (0, 15) are described in the table below. at (0, 15) are described in the table below.
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| Parameter | Normal Position | DSP (0, 15) | | Parameter | Normal Position | DSP (0, 15) |
| | | Changes | | | | Changes |
+=======================+=======================+=======================+ +============================+=======================+=======================+
| C_REG | DSP0.CBIT_0 | | | C_REG | DSP0.CBIT_0 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| A_REG | DSP0.CBIT_1 | | | A_REG | DSP0.CBIT_1 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| B_REG | DSP0.CBIT_2 | | | B_REG | DSP0.CBIT_2 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| D_REG | DSP0.CBIT_3 | | | D_REG | DSP0.CBIT_3 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| TOP_8x8_MULT_REG | DSP0.CBIT_4 | | | TOP_8x8_MULT_REG | DSP0.CBIT_4 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| BOT_8x8_MULT_REG | DSP0.CBIT_5 | | | BOT_8x8_MULT_REG | DSP0.CBIT_5 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| PIP | DSP0.CBIT_6 | | | PIPELINE_16x16_MULT_REG1 | DSP0.CBIT_6 | |
| ELINE_16x16_MULT_REG1 | | | +----------------------------+-----------------------+-----------------------+
+-----------------------+-----------------------+-----------------------+ | PIPELINE_16x16_MULT_REG2 | DSP0.CBIT_7 | |
| PIP | DSP0.CBIT_7 | | +----------------------------+-----------------------+-----------------------+
| ELINE_16x16_MULT_REG2 | | | | TOPOUTPUT_SELECT[0] | DSP1.CBIT_0 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| TOPOUTPUT_SELECT[0] | DSP1.CBIT_0 | | | TOPOUTPUT_SELECT[1] | DSP1.CBIT_1 | (0, 19).CBIT_3 |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| TOPOUTPUT_SELECT[1] | DSP1.CBIT_1 | (0, 19).CBIT_3 | | TOPADDSUB_LOWERINPUT[1:0] | DSP1.CBIT\_[3:2] | (0, 19).CBIT\_[5:4] |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| TOPA | DSP1.CBIT\_[3:2] | (0, 19).CBIT\_[5:4] | | TOPADDSUB_UPPERINUT | DSP1.CBIT_4 | (0, 19).CBIT_6 |
| DDSUB_LOWERINPUT[1:0] | | | +----------------------------+-----------------------+-----------------------+
+-----------------------+-----------------------+-----------------------+ | TOPADDSUB_CARRYSELECT[1:0] | DSP1.CBIT\_[6:5] | |
| TOPADDSUB_UPPERINUT | DSP1.CBIT_4 | (0, 19).CBIT_6 | +----------------------------+-----------------------+-----------------------+
+-----------------------+-----------------------+-----------------------+ | BOTOUTPUT_SELECT[0] | DSP1.CBIT_7 | |
| TOPAD | DSP1.CBIT\_[6:5] | | +----------------------------+-----------------------+-----------------------+
| DSUB_CARRYSELECT[1:0] | | | | BOTOUTPUT_SELECT[1] | DSP2.CBIT_0 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| BOTOUTPUT_SELECT[0] | DSP1.CBIT_7 | | | BOTADDSUB_LOWERINPUT[1:0] | DSP2.CBIT\_[2:1] | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| BOTOUTPUT_SELECT[1] | DSP2.CBIT_0 | | | BOTADDSUB_UPPERINPUT | DSP2.CBIT_3 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| BOTA | DSP2.CBIT\_[2:1] | | | BOTADDSUB_CARRYSELECT[1:0] | DSP2.CBIT\_[5:4] | |
| DDSUB_LOWERINPUT[1:0] | | | +----------------------------+-----------------------+-----------------------+
+-----------------------+-----------------------+-----------------------+ | MODE_8x8 | DSP2.CBIT_6 | |
| BOTADDSUB_UPPERINPUT | DSP2.CBIT_3 | | +----------------------------+-----------------------+-----------------------+
+-----------------------+-----------------------+-----------------------+ | A_SIGNED | DSP2.CBIT_7 | |
| BOTAD | DSP2.CBIT\_[5:4] | | +----------------------------+-----------------------+-----------------------+
| DSUB_CARRYSELECT[1:0] | | | | B_SIGNED | DSP3.CBIT_0 | |
+-----------------------+-----------------------+-----------------------+ +----------------------------+-----------------------+-----------------------+
| MODE_8x8 | DSP2.CBIT_6 | |
+-----------------------+-----------------------+-----------------------+
| A_SIGNED | DSP2.CBIT_7 | |
+-----------------------+-----------------------+-----------------------+
| B_SIGNED | DSP3.CBIT_0 | |
+-----------------------+-----------------------+-----------------------+
Lattice document a limited number of supported configurations in the ICE Lattice document a limited number of supported configurations in the ICE
Technology Library document, and Lattice's EDIF parser will reject Technology Library document, and Lattice's EDIF parser will reject