mirror of https://github.com/YosysHQ/icestorm.git
Fixed icebox_vlog handling of negclk RAM40
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parent
001eef0863
commit
9addea6cb9
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@ -699,6 +699,12 @@ for tile in ic.ramb_tiles:
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for tile in ic.ramb_tiles:
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for tile in ic.ramb_tiles:
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ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1]))
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ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1]))
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ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1]+1))
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ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1]+1))
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if ic.device == "8k":
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negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
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negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1"
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else:
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negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
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negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1"
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def get_ram_config(name):
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def get_ram_config(name):
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assert name in ram_config_bitidx
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assert name in ram_config_bitidx
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if ram_config_bitidx[name][0] == 'B':
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if ram_config_bitidx[name][0] == 'B':
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@ -723,7 +729,7 @@ for tile in ic.ramb_tiles:
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if get_ram_config('PowerUp') == (ic.device == "8k"):
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if get_ram_config('PowerUp') == (ic.device == "8k"):
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if not strip_comments:
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if not strip_comments:
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text_func.append("// RAM TILE %d %d" % tile)
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text_func.append("// RAM TILE %d %d" % tile)
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text_func.append("SB_RAM40_4K #(");
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text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else ""));
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text_func.append(" .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0)));
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text_func.append(" .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0)));
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text_func.append(" .WRITE_MODE(%d)," % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0)));
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text_func.append(" .WRITE_MODE(%d)," % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0)));
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for i in range(16):
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for i in range(16):
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@ -736,10 +742,10 @@ for tile in ic.ramb_tiles:
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text_func.append(" .RDATA(%s)," % get_ram_wire('RDATA', 15, 0, "-"))
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text_func.append(" .RDATA(%s)," % get_ram_wire('RDATA', 15, 0, "-"))
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text_func.append(" .WE(%s)," % get_ram_wire('WE', 0, 0))
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text_func.append(" .WE(%s)," % get_ram_wire('WE', 0, 0))
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text_func.append(" .WCLKE(%s)," % get_ram_wire('WCLKE', 0, 0, "1'b1"))
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text_func.append(" .WCLKE(%s)," % get_ram_wire('WCLKE', 0, 0, "1'b1"))
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text_func.append(" .WCLK(%s)," % get_ram_wire('WCLK', 0, 0))
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text_func.append(" .WCLK%s(%s)," % ("N" if negclk_wr else "", get_ram_wire('WCLK', 0, 0)))
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text_func.append(" .RE(%s)," % get_ram_wire('RE', 0, 0))
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text_func.append(" .RE(%s)," % get_ram_wire('RE', 0, 0))
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text_func.append(" .RCLKE(%s)," % get_ram_wire('RCLKE', 0, 0, "1'b1"))
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text_func.append(" .RCLKE(%s)," % get_ram_wire('RCLKE', 0, 0, "1'b1"))
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text_func.append(" .RCLK(%s)" % get_ram_wire('RCLK', 0, 0))
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text_func.append(" .RCLK%s(%s)" % ("N" if negclk_rd else "", get_ram_wire('RCLK', 0, 0)))
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text_func.append(");")
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text_func.append(");")
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text_func.append("")
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text_func.append("")
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