mirror of https://github.com/YosysHQ/icestorm.git
Split the hardware specific gpio functions.
This commit is contained in:
parent
61bc31bbdc
commit
8d9fa0fc77
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@ -84,6 +84,34 @@ enum flash_cmd {
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FC_RESET = 0x99, /* Reset Device */
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};
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// ---------------------------------------------------------
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// Hardware specific CS, CReset, CDone functions
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// ---------------------------------------------------------
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static void set_cs_creset(int cs_b, int creset_b)
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{
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uint8_t gpio = 0;
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uint8_t direction = 0x93;
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if (cs_b) {
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// ADBUS4 (GPIOL0)
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gpio |= 0x10;
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}
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if (creset_b) {
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// ADBUS7 (GPIOL3)
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gpio |= 0x80;
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}
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mpsse_set_gpio(gpio, direction);
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}
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static bool get_cdone(void)
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{
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// ADBUS6 (GPIOL2)
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return (mpsse_readb_low() & 0x40) != 0;
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}
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// ---------------------------------------------------------
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// FLASH function implementations
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// ---------------------------------------------------------
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@ -91,20 +119,20 @@ enum flash_cmd {
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// the FPGA reset is released so also FLASH chip select should be deasserted
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static void flash_release_reset()
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{
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mpsse_set_gpio(1, 1);
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set_cs_creset(1, 1);
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}
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// FLASH chip select assert
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// should only happen while FPGA reset is asserted
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static void flash_chip_select()
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{
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mpsse_set_gpio(0, 0);
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set_cs_creset(0, 0);
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}
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// FLASH chip select deassert
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static void flash_chip_deselect()
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{
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mpsse_set_gpio(1, 0);
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set_cs_creset(1, 0);
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}
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// SRAM reset is the same as flash_chip_select()
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@ -112,14 +140,14 @@ static void flash_chip_deselect()
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static void sram_reset()
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{
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// Asserting chip select and reset lines
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mpsse_set_gpio(0, 0);
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set_cs_creset(0, 0);
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}
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// SRAM chip select assert
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// When accessing FPGA SRAM the reset should be released
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static void sram_chip_select()
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{
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mpsse_set_gpio(0, 1);
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set_cs_creset(0, 1);
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}
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static void flash_read_id()
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@ -741,7 +769,7 @@ int main(int argc, char **argv)
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mpsse_init(ifnum, devstr, slow_clock);
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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flash_release_reset();
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usleep(100000);
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@ -753,7 +781,7 @@ int main(int argc, char **argv)
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flash_chip_deselect();
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usleep(250000);
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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flash_reset();
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flash_power_up();
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@ -765,7 +793,7 @@ int main(int argc, char **argv)
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flash_release_reset();
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usleep(250000);
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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}
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else if (prog_sram)
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{
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@ -781,7 +809,7 @@ int main(int argc, char **argv)
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sram_chip_select();
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usleep(2000);
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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// ---------------------------------------------------------
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@ -802,7 +830,7 @@ int main(int argc, char **argv)
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mpsse_send_dummy_bytes(6);
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mpsse_send_dummy_bit();
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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}
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else /* program flash */
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{
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@ -815,7 +843,7 @@ int main(int argc, char **argv)
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flash_chip_deselect();
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usleep(250000);
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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flash_reset();
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flash_power_up();
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@ -917,10 +945,10 @@ int main(int argc, char **argv)
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flash_power_down();
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mpsse_set_gpio(1, 1);
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set_cs_creset(1, 1);
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usleep(250000);
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fprintf(stderr, "cdone: %s\n", mpsse_get_cdone() ? "high" : "low");
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fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low");
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}
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if (f != NULL && f != stdin && f != stdout)
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@ -231,34 +231,28 @@ uint8_t mpsse_xfer_spi_bits(uint8_t data, int n)
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return mpsse_recv_byte();
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}
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void mpsse_set_gpio(int slavesel_b, int creset_b)
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void mpsse_set_gpio(uint8_t gpio, uint8_t direction)
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{
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uint8_t gpio = 0;
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if (slavesel_b) {
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// ADBUS4 (GPIOL0)
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gpio |= 0x10;
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}
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if (creset_b) {
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// ADBUS7 (GPIOL3)
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gpio |= 0x80;
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}
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mpsse_send_byte(MC_SETB_LOW);
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mpsse_send_byte(gpio); /* Value */
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mpsse_send_byte(0x93); /* Direction */
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mpsse_send_byte(direction); /* Direction */
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}
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int mpsse_get_cdone()
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int mpsse_readb_low(void)
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{
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uint8_t data;
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mpsse_send_byte(MC_READB_LOW);
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data = mpsse_recv_byte();
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// ADBUS6 (GPIOL2)
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return (data & 0x40) != 0;
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return data;
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}
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int mpsse_readb_high(void)
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{
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uint8_t data;
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mpsse_send_byte(MC_READB_HIGH);
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data = mpsse_recv_byte();
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return data;
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}
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void mpsse_send_dummy_bytes(uint8_t n)
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{
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@ -27,8 +27,9 @@ void mpsse_send_byte(uint8_t data);
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void mpsse_send_spi(uint8_t *data, int n);
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void mpsse_xfer_spi(uint8_t *data, int n);
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uint8_t mpsse_xfer_spi_bits(uint8_t data, int n);
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void mpsse_set_gpio(int slavesel_b, int creset_b);
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int mpsse_get_cdone(void);
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void mpsse_set_gpio(uint8_t gpio, uint8_t direction);
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int mpsse_readb_low(void);
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int mpsse_readb_high(void);
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void mpsse_send_dummy_bytes(uint8_t n);
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void mpsse_send_dummy_bit(void);
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void mpsse_init(int ifnum, const char *devstr, bool slow_clock);
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