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Add UltraPlus info to docs

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David Shah 2017-11-19 19:32:22 +00:00
parent 548aa14997
commit 8c0fe225ca
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@ -100,6 +100,11 @@ Here is a list of currently supported parts and the corresponding options for ar
<tr><td>iCE40-HX8K-CT256</td><td>256-ball caBGA (14 x 14 mm)</td><td>0.80 mm</td><td>206</td><td>-d 8k -P ct256</td><td>-d hx8k</td></tr>
</table>
<p>
Experimental support is also included for one iCE40 UltraPlus device, the iCE40-UP5K-SG48, including support for some of
the new UltraPlus features such as DSPs, SPRAM and internal oscillators.
</p>
<p>
Current work focuses on further improving our timing analysis flow.
</p>
@ -309,6 +314,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
<li><a href="format.html">The Bitstream File Format</a></li>
<li><a href="bitdocs-1k/">The iCE40 HX1K Bit Docs</a></li>
<li><a href="bitdocs-8k/">The iCE40 HX8K Bit Docs</a></li>
<li><a href="ultraplus.html">Notes on UltraPlus features</a></li>
</ul>
<p>