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HLC: Use '~>' instead of '<->' for routing switches. 

As mentioned in ca6b2d9ebd, the 'routing'
switches are not actually bidirectional. This makes the '<->' specifier
very misleading.

Instead use '~>' to differentiate it from the 'buffer' switches.
This commit is contained in:
Tim 'mithro' Ansell 2018-06-12 19:15:17 -07:00
parent d8d30fa630
commit 82f2f3d278
2 changed files with 7 additions and 7 deletions
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2
icebox/icebox_asc2hlc.py
View File

@ -797,7 +797,7 @@ class Tile:
self.ic.max_y - 1, entry[3])
if dst == 'fabout':
dst = lookup_fabout(*self.xy)
self.buffer_and_routing.add((src, '<->', dst))
self.buffer_and_routing.add((src, '~>', dst))
continue
if entry[1] == 'buffer':
if match:

12
icebox/icebox_hlc2asc.py
View File

@ -775,7 +775,7 @@ clearing:{:<30} - current set :{}""".format(
if (src, dst) not in self.buffers:
self.buffers.append((src, dst))
self.apply_directive('buffer', src, dst)
elif len(fields) == 3 and fields[1] == '<->':
elif len(fields) == 3 and fields[1] == '~>':
src = untranslate_netname(self.x, self.y,
self.ic.max_x - 1,
self.ic.max_y - 1, fields[0])
@ -786,7 +786,7 @@ clearing:{:<30} - current set :{}""".format(
if (src, dst) not in self.routings:
self.routings.append((src, dst))
self.apply_directive('routing', src, dst)
elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '<->'):
elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '~>'):
self.read(fields[:3])
self.read(fields[2:])
else:
@ -840,11 +840,11 @@ class LogicCell:
self.seq_bits[2] = '1'
elif fields == ['async_setreset']:
self.seq_bits[3] = '1'
elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'):
elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'):
self.read(fields[:3])
self.read(fields[2:])
return
elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'):
elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'):
prefix = 'lutff_%d/' % self.index
# Strip prefix if it is given
@ -1001,10 +1001,10 @@ class IOBlock:
== ("padin_glb_netwk", fields[2][10:])]
assert len(bit) == 1
self.tile.ic.extra_bits.add(bit[0])
elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'):
elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'):
self.read(fields[:3])
self.read(fields[2:])
elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'):
elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'):
prefix = 'io_%d/' % self.index
# Strip prefix if it is given