mirror of https://github.com/YosysHQ/icestorm.git
Merge pull request #119 from daveshah1/up5k_improve
UltraPlus Timing Analysis Improvements
This commit is contained in:
Clifford Wolf
GitHub
commit
722790ad3c
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@ -11,3 +11,4 @@ bitdata_*.txt
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data_*.txt
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database_*.txt
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timings_*.html
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tmedges_unrenamed.tmp
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@ -77,7 +77,7 @@ endif
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timings:
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ifeq ($(DEVICECLASS),5k)
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cp tmedges.txt tmedges.tmp
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set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; done
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set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; python3 rename_dsps.py $$f; done
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sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
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python3 timings.py -t timings_up5k.txt work_*/*.sdf > timings_up5k.new
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mv timings_up5k.new timings_up5k.txt
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@ -183,6 +183,10 @@ case "${ICEDEV:-hx1k-tq144}" in
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iCEPACKAGE="SG48"
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iCE40DEV="iCE40UP5K"
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;;
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up5k-uwg30)
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iCEPACKAGE="UWG30"
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iCE40DEV="iCE40UP5K"
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;;
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*)
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echo "ERROR: Invalid \$ICEDEV device config '$ICEDEV'."
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exit 1
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@ -379,8 +383,8 @@ cat > foobar_sbt.project << EOT
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Implementations=foobar_Implmnt
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[foobar_Implmnt]
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DeviceFamily=$( echo $iCE40DEV | sed -re 's,(HX).*,,'; )
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Device=$( echo $iCE40DEV | sed -re 's,iCE40,,'; )
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DeviceFamily=$( echo $iCE40DEV | sed -re 's,(HX|5K).*,,'; )
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Device=$( echo $iCE40DEV | sed -re 's,iCE40(UP)?,,'; )
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DevicePackage=$iCEPACKAGE
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Devicevoltage=1.14
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DevicevoltagePerformance=+/-5%(datasheet default)
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@ -419,4 +423,3 @@ fi
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export LD_LIBRARY_PATH=""
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$scriptdir/../icepack/iceunpack "$1.bin" "$1.asc"
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@ -19,14 +19,41 @@ def randbin(n):
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#Only certain combinations are allowed in icecube, list them here
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#This is not a complete set, but enough to cover all bits except cbit13, which
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#is not set in any allowed config (?)
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allowed_configs = ["0010000010000001001110110", "1110000010000001001110110", "0010000010000001000000000", "1110000010000001000000000",
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"0000000011000001111110110", "1100000011000001111110110", "0000000011000001110000110", "0010000101000010111111111",
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"0000001001100100111111111", "0001001001100100111111111", "0001101001100100111111111", "0001111000101100000000000"]
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allowed_configs = [("0010000010000001001110110", "SB_MAC16_MUL_U_8X8_ALL_PIPELINE"),
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("1110000010000001001110110", "SB_MAC16_MUL_S_8X8_ALL_PIPELINE"),
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("0010000010000001000000000", "SB_MAC16_MUL_U_8X8_BYPASS"),
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("1110000010000001000000000", "SB_MAC16_MUL_S_8X8_BYPASS"),
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("0000000011000001111110110", "SB_MAC16_MUL_U_16X16_ALL_PIPELINE"),
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("1100000011000001111110110", "SB_MAC16_MUL_S_16X16_ALL_PIPELINE"),
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("0000000011000001110000110", "SB_MAC16_MUL_U_16X16_IM_BYPASS"),
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("1100000011000001110000110", "SB_MAC16_MUL_S_16X16_IM_BYPASS"),
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("0000000011000001100000000", "SB_MAC16_MUL_U_16X16_BYPASS"),
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("1100000011000001100000000", "SB_MAC16_MUL_S_16X16_BYPASS"),
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("0010000101000010111111111", "SB_MAC16_MAC_U_8X8_ALL_PIPELINE"),
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("0010000101000010100001111", "SB_MAC16_MAC_U_8X8_IM_BYPASS"),
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("0010000101000010100000000", "SB_MAC16_MAC_U_8X8_BYPASS"),
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("0000001001100100111111111", "SB_MAC16_MAC_U_16X16_ALL_PIPELINE"),
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("0001001001100100111111111", "SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE"),
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("0001101001100100111111111", "SB_MAC16_MAC_U_16X16_CIN_ALL_PIPELINE"),
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("0000001001100100110001111", "SB_MAC16_MAC_U_16X16_IM_BYPASS"),
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("0000001001100100100000000", "SB_MAC16_MAC_U_16X16_BYPASS"),
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("1100001001100100110001111", "SB_MAC16_MAC_S_16X16_IM_BYPASS"),
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("0010000001000000100001111", "SB_MAC16_ACC_U_16P16_ALL_PIPELINE"),
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("0010000001000000100000000", "SB_MAC16_ACC_U_16P16_BYPASS"),
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("0010000001100000100001111", "SB_MAC16_ACC_U_32P32_ALL_PIPELINE"),
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("0010000001100000100000000", "SB_MAC16_ACC_U_32P32_BYPASS"),
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("0010010001001000100001111", "SB_MAC16_ADS_U_16P16_ALL_PIPELINE"),
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("0010010000001000000000000", "SB_MAC16_ADS_U_16P16_BYPASS"),
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("0010010001101000100001111", "SB_MAC16_ADS_U_32P32_ALL_PIPELINE"),
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("0010010000101000000000000", "SB_MAC16_ADS_U_32P32_BYPASS"),
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("0010010101001010111111111", "SB_MAC16_MAS_U_8X8_ALL_PIPELINE")]
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coverage = set()
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for c in allowed_configs:
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cfg, name = c
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for i in range(25):
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if c[i] == "1":
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if cfg[i] == "1":
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coverage.add(i)
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assert len(coverage) >= 24
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@ -37,6 +64,13 @@ assert len(coverage) >= 24
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for idx in range(num):
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with open(working_dir + "/dsp_%02d.v" % idx, "w") as f:
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glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)]
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config = allowed_configs[np.random.randint(len(allowed_configs))]
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params, cfgname = config
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with open(working_dir + "/dsp_%02d.dsp" % idx, "w") as dspf:
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dspf.write(cfgname + "\n")
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params = params[::-1]
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# TODO: ce should be on this list, but causes routing failures
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glbs_choice = ["clk", "a", "b", "c", "d,", "ah", "bh", "ch", "dh", "irt", "irb", "ort", "orb", "olt", "olb", "ast", "asb", "oht", "ohb", "sei"]
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print("""
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@ -118,8 +152,7 @@ for idx in range(num):
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bits_d = "{%s}" % ", ".join(bits_d)
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negclk = randbin(1)
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params = np.random.choice(allowed_configs)
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params = params[::-1]
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print("""
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wire [34:0] out_%d;
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SB_MAC16 #(
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@ -0,0 +1,19 @@
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#!/usr/bin/env python3
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import sys, os
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dsptype = None
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dsppath = sys.argv[1].replace(".vsb", ".dsp")
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if os.path.exists(dsppath):
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with open(dsppath, 'r') as f:
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dsptype = f.readline().strip()
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with open("tmedges.tmp", "a") as outfile:
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with open("tmedges_unrenamed.tmp", "r") as infile:
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for line in infile:
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if "SB_MAC16" in line:
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if dsptype is not None:
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outfile.write(line.replace("SB_MAC16", dsptype))
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else:
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outfile.write(line)
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@ -227,6 +227,12 @@ for filename in sdf_inputs:
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for stmt in cell:
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if stmt[0] == "CELLTYPE":
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celltype = rewrite_celltype(stmt[1][1:-1])
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if celltype == "SB_MAC16":
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try:
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with open(filename.replace(".sdf", ".dsp"), "r") as dspf:
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celltype = dspf.readline().strip()
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except:
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break
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database.setdefault(celltype, set())
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if stmt[0] == "DELAY":
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@ -0,0 +1,5 @@
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while true; do
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rm -rf data_5k_*.txt work_5k_*
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make DEVICECLASS=5k -j3
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make DEVICECLASS=5k timings
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done
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16416
icefuzz/timings_up5k.txt
16416
icefuzz/timings_up5k.txt
File diff suppressed because it is too large
Load Diff
5043
icefuzz/tmedges.txt
5043
icefuzz/tmedges.txt
File diff suppressed because it is too large
Load Diff
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@ -29,4 +29,4 @@ hierarchy -generate gio2CtrlBuf i:I o:O
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hierarchy -generate CascadeBuf i:I o:O
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hierarchy -check
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tee -a tmedges.tmp edgetypes
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tee -o tmedges_unrenamed.tmp edgetypes
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@ -104,7 +104,11 @@ std::set<int> declared_nets;
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int dangling_cnt = 0;
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std::map<std::string, std::vector<std::pair<int, int>>> logic_tile_bits,
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io_tile_bits, ramb_tile_bits, ramt_tile_bits;
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io_tile_bits, ramb_tile_bits, ramt_tile_bits, ipcon_tile_bits, dsp0_tile_bits,
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dsp1_tile_bits, dsp2_tile_bits, dsp3_tile_bits;
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std::map<std::tuple<std::string, int, int, int>,
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std::map<std::string, std::tuple<int, int, std::string>>> extra_cells;
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std::string vstringf(const char *fmt, va_list ap)
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{
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@ -328,8 +332,9 @@ void read_chipdb()
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std::string mode;
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int current_net = -1;
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int tile_x = -1, tile_y = -1;
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int tile_x = -1, tile_y = -1, cell_z = -1;
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std::string thiscfg;
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std::string cellname;
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std::vector<std::vector<int>> gbufin;
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std::vector<std::vector<int>> gbufpin;
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@ -377,6 +382,22 @@ void read_chipdb()
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continue;
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}
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if (mode == ".extra_cell") {
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tile_x = atoi(strtok(nullptr, " \t\r\n"));
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tile_y = atoi(strtok(nullptr, " \t\r\n"));
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// For legacy reasons, extra_cell may be X Y name or X Y Z name
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const char *z_or_name = strtok(nullptr, " \t\r\n");
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if(isdigit(z_or_name[0])) {
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cell_z = atoi(z_or_name);
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cellname = std::string(strtok(nullptr, " \t\r\n"));
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} else {
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cell_z = 0;
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cellname = std::string(z_or_name);
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}
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extra_cells[std::make_tuple(cellname, tile_x, tile_y, cell_z)] = {};
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continue;
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}
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continue;
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}
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@ -432,7 +453,8 @@ void read_chipdb()
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gbufpin.push_back(items);
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}
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if (mode == ".logic_tile_bits" || mode == ".io_tile_bits" || mode == ".ramb_tile_bits" || mode == ".ramt_tile_bits") {
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if (mode == ".logic_tile_bits" || mode == ".io_tile_bits" || mode == ".ramb_tile_bits" || mode == ".ramt_tile_bits" ||
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mode == ".ipcon_tile_bits" || mode == ".dsp0_tile_bits" || mode == ".dsp1_tile_bits" || mode == ".dsp2_tile_bits" || mode == ".dsp3_tile_bits") {
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std::vector<std::pair<int, int>> items;
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while (1) {
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const char *s = strtok(nullptr, " \t\r\n");
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@ -451,6 +473,16 @@ void read_chipdb()
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ramb_tile_bits[tok] = items;
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if (mode == ".ramt_tile_bits")
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ramt_tile_bits[tok] = items;
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if (mode == ".ipcon_tile_bits")
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ipcon_tile_bits[tok] = items;
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if (mode == ".dsp0_tile_bits")
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dsp0_tile_bits[tok] = items;
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if (mode == ".dsp1_tile_bits")
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dsp1_tile_bits[tok] = items;
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if (mode == ".dsp2_tile_bits")
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dsp2_tile_bits[tok] = items;
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if (mode == ".dsp3_tile_bits")
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dsp3_tile_bits[tok] = items;
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}
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if (mode == ".extra_bits") {
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@ -461,6 +493,17 @@ void read_chipdb()
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if (extra_bits.count(key))
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extrabitfunc.insert(tok);
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}
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if(mode == ".extra_cell") {
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std::string key = std::string(tok);
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if(key != "LOCKED") {
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int x = atoi(strtok(nullptr, " \t\r\n"));
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int y = atoi(strtok(nullptr, " \t\r\n"));
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std::string name = std::string(strtok(nullptr, " \t\r\n"));
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extra_cells[make_tuple(cellname, tile_x, tile_y, cell_z)][key] = make_tuple(x, y, name);
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}
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}
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}
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fclose(fdb);
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@ -559,6 +602,14 @@ bool is_primary(std::string cell_name, std::string out_port)
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if (cell_type == "PRE_IO")
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return true;
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if (cell_type == "SB_SPRAM256KA")
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return true;
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std::string dsp_prefix = "SB_MAC16";
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if(cell_type.substr(0, dsp_prefix.length()) == dsp_prefix)
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return (cell_type != "SB_MAC16_MUL_U_16X16_BYPASS" && cell_type != "SB_MAC16_MUL_U_8X8_BYPASS"
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&& cell_type != "SB_MAC16_ADS_U_16P16_BYPASS" && cell_type != "SB_MAC16_ADS_U_32P32_BYPASS");
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return false;
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}
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@ -647,14 +698,42 @@ const std::set<std::string> &get_inports(std::string cell_type)
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inports_map["SB_RAM40_4K"].insert(stringf("WADDR[%d]", i));
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}
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inports_map["SB_MAC16"] = { "CLK", "CE", "AHOLD", "BHOLD", "CHOLD", "DHOLD", "IRSTTOP", "IRSTBOT", "ORSTTOP", "ORSTBOT",
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"OLOADTOP", "OLOADBOT", "ADDSUBTOP", "ADDSUBBOT", "OHOLDTOP", "OHOLDBOT", "CI", "ACCUMCI",
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"SIGNEXTIN"};
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for (int i = 0; i < 16; i++) {
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inports_map["SB_MAC16"].insert(stringf("C[%d]", i));
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inports_map["SB_MAC16"].insert(stringf("A[%d]", i));
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inports_map["SB_MAC16"].insert(stringf("B[%d]", i));
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inports_map["SB_MAC16"].insert(stringf("D[%d]", i));
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}
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inports_map["SB_SPRAM256KA"] = { "WREN", "CHIPSELECT", "CLOCK", "STANDBY", "SLEEP", "POWEROFF",
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"MASKWREN[0]", "MASKWREN[1]", "MASKWREN[2]", "MASKWREN[3]"};
|
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|
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for (int i = 0; i < 16; i++) {
|
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inports_map["SB_SPRAM256KA"].insert(stringf("DATAIN[%d]", i));
|
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}
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for (int i = 0; i < 14; i++) {
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inports_map["SB_SPRAM256KA"].insert(stringf("ADDRESS[%d]", i));
|
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}
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|
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inports_map["INTERCONN"] = { "I" };
|
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}
|
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|
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|
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std::string dsp_prefix = "SB_MAC16";
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|
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if(cell_type.substr(0, dsp_prefix.length()) == dsp_prefix)
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cell_type = "SB_MAC16";
|
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|
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if (inports_map.count(cell_type) == 0) {
|
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fprintf(stderr, "Missing entry in inports_map for cell type %s!\n", cell_type.c_str());
|
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exit(1);
|
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}
|
||||
|
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|
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return inports_map.at(cell_type);
|
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}
|
||||
|
||||
|
|
@ -679,7 +758,7 @@ double get_delay(std::string cell_type, std::string in_port, std::string out_por
|
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|
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if (device_type == "hx8k")
|
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return get_delay_hx8k(cell_type, in_port, out_port);
|
||||
|
||||
|
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if (device_type == "up5k")
|
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return get_delay_up5k(cell_type, in_port, out_port);
|
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fprintf(stderr, "No built-in timing database for '%s' devices!\n", device_type.c_str());
|
||||
|
|
@ -1182,6 +1261,174 @@ std::string make_lc40(int x, int y, int z)
|
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return cell;
|
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}
|
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|
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bool get_dsp_ip_cbit(std::tuple<int, int, std::string> cbit) {
|
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std::string name = "IpConfig." + std::get<2>(cbit);
|
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// DSP0 contains all CBITs, the same as any DSP/IP tile
|
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if(dsp0_tile_bits.count(name)) {
|
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auto bitpos = dsp0_tile_bits.at(name)[0];
|
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return config_bits[std::get<0>(cbit)][std::get<1>(cbit)][bitpos.first][bitpos.second];
|
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}
|
||||
return false;
|
||||
}
|
||||
|
||||
std::string ecnetname_to_vlog(std::string ec_name)
|
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{
|
||||
// Convert a net name from the form A_0 used in the chipdb for extra cells to
|
||||
// verilog form A[0]
|
||||
size_t last_ = ec_name.find_last_of('_');
|
||||
if(last_ == std::string::npos)
|
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return ec_name;
|
||||
|
||||
std::string base = ec_name.substr(0, last_);
|
||||
std::string end = ec_name.substr(last_+1);
|
||||
size_t nidx = 0;
|
||||
|
||||
int num = std::stoi(end, &nidx, 10);
|
||||
if(nidx == end.length()) {
|
||||
return base + "[" + std::to_string(num) + "]";
|
||||
} else {
|
||||
return ec_name;
|
||||
}
|
||||
}
|
||||
|
||||
std::string make_dsp_ip(int x, int y, std::string net, std::string &primnet)
|
||||
{
|
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std::tuple<int, int, std::string> ecnet(x, y, net);
|
||||
std::tuple<std::string, int, int, int> key("", -1, -1, -1);
|
||||
bool found = false;
|
||||
for(auto ec : extra_cells) {
|
||||
for(auto entry : ec.second) {
|
||||
if(entry.second == ecnet) {
|
||||
key = ec.first;
|
||||
primnet = ecnetname_to_vlog(entry.first);
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if(!found) {
|
||||
fprintf(stderr, "Error: net (%d, %d, '%s') does not correspond to any IP\n", x, y, net.c_str());
|
||||
exit(1);
|
||||
}
|
||||
int cx, cy, cz;
|
||||
std::string ectype;
|
||||
std::tie(ectype, cx, cy, cz) = key;
|
||||
|
||||
auto cell = stringf("%s_%d_%d_%d", ectype.c_str(), cx, cy, cz);
|
||||
|
||||
if (netlist_cell_types.count(cell))
|
||||
return cell;
|
||||
|
||||
if(ectype == "MAC16") {
|
||||
// Given the few actual unique timing possibilites, only look at a subset
|
||||
// of the CBITs to pick the closest cell type from a timing point of view
|
||||
std::string dsptype = "";
|
||||
bool mode_8x8 = get_dsp_ip_cbit(extra_cells[key].at("MODE_8x8"));
|
||||
// It seems no different between any pipeline mode, so pick pipelining based
|
||||
// on one of the bits
|
||||
bool pipeline = get_dsp_ip_cbit(extra_cells[key].at("A_REG"));
|
||||
int botout = (get_dsp_ip_cbit(extra_cells[key].at("BOTOUTPUT_SELECT_1")) << 1) | get_dsp_ip_cbit(extra_cells[key].at("BOTOUTPUT_SELECT_0"));
|
||||
int botlwrin = (get_dsp_ip_cbit(extra_cells[key].at("BOTADDSUB_LOWERINPUT_1")) << 1) | get_dsp_ip_cbit(extra_cells[key].at("BOTADDSUB_LOWERINPUT_0"));
|
||||
bool botuprin = get_dsp_ip_cbit(extra_cells[key].at("BOTADDSUB_UPPERINPUT"));
|
||||
int topcarry = (get_dsp_ip_cbit(extra_cells[key].at("TOPADDSUB_CARRYSELECT_1")) << 1) | get_dsp_ip_cbit(extra_cells[key].at("TOPADDSUB_CARRYSELECT_0"));
|
||||
// Worst case default
|
||||
std::string basename = "SB_MAC16_MUL_U_16X16";
|
||||
// Note: signedness is ignored as it seems to have no effect
|
||||
if(mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 2)) {
|
||||
basename = "SB_MAC16_MUL_U_8X8";
|
||||
} else if (!mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 3)) {
|
||||
basename = "SB_MAC16_MUL_U_16X16";
|
||||
} else if (mode_8x8 && !botuprin && (botlwrin == 1) && (botout == 1)) {
|
||||
basename = "SB_MAC16_MAC_U_8X8";
|
||||
} else if (!mode_8x8 && !botuprin && (botlwrin == 2) && (botout == 1)) {
|
||||
basename = "SB_MAC16_MAC_U_16X16";
|
||||
} else if (mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 1) && (topcarry == 0)) {
|
||||
basename = "SB_MAC16_ACC_U_16P16";
|
||||
} else if (mode_8x8 && !botuprin && (botlwrin == 0) && (botout == 1) && (topcarry == 2)) {
|
||||
basename = "SB_MAC16_ACC_U_32P32";
|
||||
} else if (mode_8x8 && botuprin && (botlwrin == 0) && (topcarry == 0)) {
|
||||
basename = "SB_MAC16_ADS_U_16P16";
|
||||
} else if (mode_8x8 && botuprin && (botlwrin == 0) && (topcarry == 2)) {
|
||||
basename = "SB_MAC16_ADS_U_32P32";
|
||||
} else if (mode_8x8 && botuprin && (botlwrin == 1)) {
|
||||
basename = "SB_MAC16_MAS_U_8X8";
|
||||
} else if (!mode_8x8 && botuprin && (botlwrin == 2)) {
|
||||
basename = "SB_MAC16_MAS_U_16X16";
|
||||
} else {
|
||||
fprintf(stderr, "Warning: detected unknown/unsupported DSP config, defaulting to 16x16 MUL.\n");
|
||||
}
|
||||
dsptype = basename + (pipeline ? "_ALL_PIPELINE" : "_BYPASS");
|
||||
netlist_cell_types[cell] = dsptype;
|
||||
|
||||
for (int i = 0; i < 16; i++) {
|
||||
netlist_cell_ports[cell][stringf("C[%d]", i)] = "gnd";
|
||||
netlist_cell_ports[cell][stringf("A[%d]", i)] = "gnd";
|
||||
netlist_cell_ports[cell][stringf("B[%d]", i)] = "gnd";
|
||||
netlist_cell_ports[cell][stringf("D[%d]", i)] = "gnd";
|
||||
}
|
||||
|
||||
netlist_cell_ports[cell]["CLK"] = "";
|
||||
netlist_cell_ports[cell]["CE"] = "";
|
||||
netlist_cell_ports[cell]["AHOLD"] = "gnd";
|
||||
netlist_cell_ports[cell]["BHOLD"] = "gnd";
|
||||
netlist_cell_ports[cell]["CHOLD"] = "gnd";
|
||||
netlist_cell_ports[cell]["DHOLD"] = "gnd";
|
||||
|
||||
netlist_cell_ports[cell]["IRSTTOP"] = "";
|
||||
netlist_cell_ports[cell]["IRSTBOT"] = "";
|
||||
netlist_cell_ports[cell]["ORSTTOP"] = "";
|
||||
netlist_cell_ports[cell]["ORSTBOT"] = "";
|
||||
|
||||
netlist_cell_ports[cell]["OLOADTOP"] = "gnd";
|
||||
netlist_cell_ports[cell]["OLOADBOT"] = "gnd";
|
||||
netlist_cell_ports[cell]["ADDSUBTOP"] = "gnd";
|
||||
netlist_cell_ports[cell]["ADDSUBBOT"] = "gnd";
|
||||
netlist_cell_ports[cell]["OHOLDTOP"] = "gnd";
|
||||
netlist_cell_ports[cell]["OHOLDBOT"] = "gnd";
|
||||
netlist_cell_ports[cell]["CI"] = "gnd";
|
||||
netlist_cell_ports[cell]["ACCUMCI"] = "";
|
||||
netlist_cell_ports[cell]["SIGNEXTIN"] = "";
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
netlist_cell_ports[cell][stringf("O[%d]", i)] = "";
|
||||
}
|
||||
|
||||
netlist_cell_ports[cell]["ACCUMCO"] = "";
|
||||
netlist_cell_ports[cell]["SIGNEXTOUT"] = "";
|
||||
|
||||
return cell;
|
||||
} else if(ectype == "SPRAM") {
|
||||
netlist_cell_types[cell] = "SB_SPRAM256KA";
|
||||
|
||||
for (int i = 0; i < 14; i++) {
|
||||
netlist_cell_ports[cell][stringf("ADDRESS[%d]", i)] = "gnd";
|
||||
}
|
||||
|
||||
for (int i = 0; i < 16; i++) {
|
||||
netlist_cell_ports[cell][stringf("DATAIN[%d]", i)] = "gnd";
|
||||
netlist_cell_ports[cell][stringf("DATAOUT[%d]", i)] = "";
|
||||
}
|
||||
|
||||
netlist_cell_ports[cell]["MASKWREN[3]"] = "gnd";
|
||||
netlist_cell_ports[cell]["MASKWREN[2]"] = "gnd";
|
||||
netlist_cell_ports[cell]["MASKWREN[1]"] = "gnd";
|
||||
netlist_cell_ports[cell]["MASKWREN[0]"] = "gnd";
|
||||
|
||||
netlist_cell_ports[cell]["WREN"] = "gnd";
|
||||
netlist_cell_ports[cell]["CHIPSELECT"] = "gnd";
|
||||
netlist_cell_ports[cell]["CLOCK"] = "";
|
||||
netlist_cell_ports[cell]["STANDBY"] = "gnd";
|
||||
netlist_cell_ports[cell]["SLEEP"] = "gnd";
|
||||
netlist_cell_ports[cell]["POWEROFF"] = "gnd";
|
||||
|
||||
return cell;
|
||||
} else {
|
||||
netlist_cell_types[cell] = "SB_" + ectype;
|
||||
fprintf(stderr, "Warning: timing analysis not supported for cell type %s\n", ectype.c_str());
|
||||
return cell;
|
||||
}
|
||||
}
|
||||
|
||||
std::string make_ram(int x, int y)
|
||||
{
|
||||
auto cell = stringf("ram_%d_%d", x, y);
|
||||
|
|
@ -1316,14 +1563,26 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
}
|
||||
|
||||
if (sscanf(seg.name.c_str(), "lutff_%d/in_%d", &a, &b) == 2) {
|
||||
auto cell = make_lc40(seg.x, seg.y, a);
|
||||
if (b == 2) {
|
||||
// Lattice tools always put a CascadeMux on in2
|
||||
netlist_cell_ports[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
|
||||
//"logic" wires at the side of the device are actually IP or DSP
|
||||
if(device_type == "up5k" && ((seg.x == 0) || (seg.x == config_tile_type.size() - 1))) {
|
||||
std::string primnet;
|
||||
auto cell = make_dsp_ip(seg.x, seg.y, seg.name, primnet);
|
||||
netlist_cell_ports[cell][primnet] = net_name(net);
|
||||
if(cell != "") {
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
netlist_cell_ports[cell][stringf("in%d", b)] = net_name(net);
|
||||
auto cell = make_lc40(seg.x, seg.y, a);
|
||||
if (b == 2) {
|
||||
// Lattice tools always put a CascadeMux on in2
|
||||
netlist_cell_ports[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
|
||||
} else {
|
||||
netlist_cell_ports[cell][stringf("in%d", b)] = net_name(net);
|
||||
}
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
}
|
||||
make_inmux(seg.x, seg.y, net);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1345,6 +1604,28 @@ void make_seg_cell(int net, const net_segment_t &seg)
|
|||
return;
|
||||
}
|
||||
|
||||
if (sscanf(seg.name.c_str(), "slf_op_%d", &a) == 1)
|
||||
{
|
||||
std::string primnet;
|
||||
auto cell = make_dsp_ip(seg.x, seg.y, seg.name, primnet);
|
||||
if(cell != "") {
|
||||
netlist_cell_ports[cell][primnet] = net_name(net);
|
||||
make_odrv(seg.x, seg.y, net);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (sscanf(seg.name.c_str(), "mult/O_%d", &a) == 1)
|
||||
{
|
||||
std::string primnet;
|
||||
auto cell = make_dsp_ip(seg.x, seg.y, seg.name, primnet);
|
||||
if(cell != "") {
|
||||
netlist_cell_ports[cell][primnet] = net_name(net);
|
||||
make_odrv(seg.x, seg.y, net);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (sscanf(seg.name.c_str(), "lutff_%d/cou%c", &a, &c) == 2 && c == 't')
|
||||
{
|
||||
auto cell = make_lc40(seg.x, seg.y, a);
|
||||
|
|
@ -2025,7 +2306,10 @@ int main(int argc, char **argv)
|
|||
read_config();
|
||||
|
||||
if (device_type.empty()) {
|
||||
device_type = "lp" + config_device;
|
||||
if(config_device == "5k")
|
||||
device_type = "up" + config_device;
|
||||
else
|
||||
device_type = "lp" + config_device;
|
||||
printf("// Warning: Missing -d parameter. Assuming '%s' device.\n", device_type.c_str());
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ def timings_to_c(chip, f):
|
|||
print("{")
|
||||
|
||||
in_cell = False
|
||||
|
||||
last_cell = ""
|
||||
for line in f:
|
||||
fields = line.split()
|
||||
if len(fields) == 0:
|
||||
|
|
@ -18,8 +18,14 @@ def timings_to_c(chip, f):
|
|||
|
||||
if fields[0] == "CELL":
|
||||
if in_cell:
|
||||
if last_cell.startswith("SB_MAC16"):
|
||||
# DSPs have incomplete timing specification, as some paths
|
||||
# don't mathematically exist - e.g. there is no path from
|
||||
# A[1] to O[0]
|
||||
print(" if (in_port != \"*clkedge*\" && out_port != \"*setup*\") return 0.0;")
|
||||
print(" }")
|
||||
print(" if (cell_type == \"%s\") {" % fields[1])
|
||||
last_cell = fields[1]
|
||||
in_cell = True
|
||||
|
||||
if fields[0] == "SETUP":
|
||||
|
|
@ -44,4 +50,3 @@ def timings_to_c(chip, f):
|
|||
for db in "lp384 lp1k lp8k hx1k hx8k up5k".split():
|
||||
with open("../icefuzz/timings_%s.txt" % db, "r") as f:
|
||||
timings_to_c(db, f);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue