mirror of https://github.com/YosysHQ/icestorm.git
icetime progress
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639624347c
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@ -28,7 +28,7 @@
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#include <map>
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#include <set>
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// add this number of ns as estimation for clock distribution mismatch
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// add this number of ns as estimate for clock distribution mismatch
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#define GLOBAL_CLK_DIST_JITTER 0.1
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FILE *fin, *fout;
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@ -638,6 +638,9 @@ struct TimingAnalysis
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std::string global_max_path_net;
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double global_max_path_delay;
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bool interior_timing;
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std::set<std::string> interior_nets;
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double calc_net_max_path_delay(const std::string &net)
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{
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if (net_max_path_delay.count(net))
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@ -646,7 +649,7 @@ struct TimingAnalysis
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if (net_driver.count(net) == 0)
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return 0;
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double max_path_delay = 0;
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double max_path_delay = -1e6;
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net_max_path_delay[net] = 1e6;
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auto &driver_cell = net_driver.at(net).first;
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@ -654,8 +657,11 @@ struct TimingAnalysis
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auto &driver_type = netlist_cell_types.at(driver_cell);
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if (is_primary(driver_cell, driver_port)) {
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net_max_path_delay[net] = get_delay(driver_type, "*clkedge*", driver_port) + GLOBAL_CLK_DIST_JITTER;
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return 0;
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if (interior_timing && driver_type == "PRE_IO")
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net_max_path_delay[net] = -1e3;
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else
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net_max_path_delay[net] = get_delay(driver_type, "*clkedge*", driver_port) + GLOBAL_CLK_DIST_JITTER;
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return net_max_path_delay[net];
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}
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for (auto &inport : get_inports(driver_type))
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@ -680,6 +686,9 @@ struct TimingAnalysis
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if (*in_net == "" || *in_net == "vcc" || *in_net == "gnd")
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continue;
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if (interior_timing && interior_nets.count(*in_net) == 0)
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continue;
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double this_cell_delay = get_delay(driver_type, inport, driver_port);
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double this_path_delay = calc_net_max_path_delay(*in_net) + this_cell_delay;
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@ -693,7 +702,33 @@ struct TimingAnalysis
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return net_max_path_delay.at(net);
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}
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TimingAnalysis()
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void mark_interior(std::string net)
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{
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while (net_assignments.count(net)) {
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interior_nets.insert(net);
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net = net_assignments.at(net);
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}
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if (interior_nets.count(net))
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return;
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interior_nets.insert(net);
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if (!net_driver.count(net))
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return;
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auto &driver_cell = net_driver.at(net).first;
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auto &driver_port = net_driver.at(net).second;
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auto &driver_type = netlist_cell_types.at(driver_cell);
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if (is_primary(driver_cell, driver_port))
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return;
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for (auto &inport : get_inports(driver_type))
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mark_interior(netlist_cell_ports.at(driver_cell).at(inport));
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}
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TimingAnalysis(bool interior_timing) : interior_timing(interior_timing)
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{
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std::set<std::string> all_nets;
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@ -719,6 +754,8 @@ struct TimingAnalysis
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break;
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n = net_assignments.at(n);
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}
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if (interior_timing && cell_type != "PRE_IO" && is_primary(cell_name, "lcout"))
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mark_interior(net_name);
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continue;
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}
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@ -1727,7 +1764,10 @@ void help(const char *cmd)
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printf(" that includes the given net to 'icetime_graph.dot'.\n");
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printf("\n");
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printf(" -m\n");
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printf(" enable max_span_hack for conservative estimates\n");
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printf(" enable max_span_hack for conservative timing estimates\n");
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printf("\n");
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printf(" -i\n");
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printf(" only consider interior timing paths (not to/from IOs)\n");
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printf("\n");
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printf(" -t\n");
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printf(" print a timing estimate (based on topological timing\n");
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@ -1745,10 +1785,11 @@ void help(const char *cmd)
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int main(int argc, char **argv)
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{
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bool print_timing = false;
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bool interior_timing = false;
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std::vector<std::string> print_timing_nets;
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int opt;
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while ((opt = getopt(argc, argv, "p:P:g:mtT:v")) != -1)
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while ((opt = getopt(argc, argv, "p:P:g:mitT:v")) != -1)
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{
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switch (opt)
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{
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@ -1765,6 +1806,9 @@ int main(int argc, char **argv)
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case 'm':
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max_span_hack = true;
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break;
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case 'i':
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interior_timing = true;
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break;
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case 't':
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print_timing = true;
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break;
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@ -1808,9 +1852,11 @@ int main(int argc, char **argv)
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printf("// Reading input .asc file..\n");
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read_config();
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printf("// Reading chipdb file..\n");
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printf("// Reading %s chipdb file..\n", config_device.c_str());
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read_chipdb();
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printf("// Creating timing netlist..\n");
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for (int net : used_nets)
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for (auto &seg : net_to_segments[net])
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make_seg_cell(net, seg);
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@ -2015,14 +2061,16 @@ int main(int argc, char **argv)
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printf("Info: max_span_hack is enabled: estimate is conservative.\n");
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printf("\n");
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TimingAnalysis ta;
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TimingAnalysis ta(interior_timing);
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for (auto &n : print_timing_nets)
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ta.report(n);
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ta.report();
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if (print_timing)
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ta.report();
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}
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else
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{
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TimingAnalysis ta;
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TimingAnalysis ta(interior_timing);
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printf("// Timing estimate: %.2f ns (%.2f MHz)\n", ta.global_max_path_delay, 1000.0 / ta.global_max_path_delay);
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}
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