mirror of https://github.com/YosysHQ/icestorm.git
Add icestick "checker" example
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@ -11,3 +11,12 @@ rs232demo_tb.vcd
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rs232demo_syn.v
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rs232demo_syntb
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rs232demo_syntb.vcd
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checker.bin
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checker.blif
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checker.asc
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checker.rpt
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checker_tb
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checker_tb.vcd
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checker_syn.v
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checker_syntb
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checker_syntb.vcd
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@ -1,5 +1,6 @@
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PROJ = example
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# PROJ = rs232demo
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# PROJ = checker
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PIN_DEF = icestick.pcf
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DEVICE = hx1k
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@ -22,16 +23,16 @@ all: $(PROJ).rpt $(PROJ).bin
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iverilog -o $@ $^
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%_tb.vcd: %_tb
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./$< +vcd=$@
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vvp -N $< +vcd=$@
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%_syn.v: %.blif
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yosys -o $@ $^
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yosys -p 'read_blif -wideports $^; write_verilog $@'
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%_syntb: %_tb.v %_syn.v
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iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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%_syntb.vcd: %_syntb
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./$< +vcd=$@
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vvp -N $< +vcd=$@
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prog: $(PROJ).bin
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iceprog $<
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@ -0,0 +1,55 @@
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// A simple circuit that can be used to detect brownouts and other hardware issues
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module top (
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input clk,
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output LED1,
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output LED2,
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output LED3,
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output LED4,
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output LED5
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);
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reg [7:0] reset_counter = 0;
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reg resetn = 0;
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always @(posedge clk) begin
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reset_counter <= reset_counter + 1;
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resetn <= resetn | &reset_counter;
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end
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reg error, rdmode, rdfin;
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reg [31:0] scratchpad [0:1023];
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reg [31:0] xorshift32_state;
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reg [9:0] index;
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reg [31:0] next_xorshift32_state;
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always @* begin
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next_xorshift32_state = xorshift32_state ^ ( xorshift32_state << 13);
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next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state >> 17);
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next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state << 5);
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end
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always @(posedge clk) begin
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xorshift32_state <= &index ? 123456789 : next_xorshift32_state;
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index <= index + 1;
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if (!resetn) begin
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xorshift32_state <= 123456789;
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index <= 0;
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error <= 0;
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rdmode <= 0;
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rdfin <= 0;
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end else
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if (!rdmode) begin
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scratchpad[index] <= xorshift32_state;
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rdmode <= &index;
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end else begin
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if (scratchpad[index] != xorshift32_state) error <= 1;
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rdfin <= rdfin || &index;
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end
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end
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wire ok = resetn && rdfin && !error;
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assign LED1 = error, LED2 = error, LED3 = error, LED4 = error, LED5 = ok;
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endmodule
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@ -0,0 +1,40 @@
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module testbench;
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reg clk;
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always #5 clk = (clk === 1'b0);
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wire ok;
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top uut (
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.clk(clk),
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.LED5(ok)
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);
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reg [4095:0] vcdfile;
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initial begin
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if ($value$plusargs("vcd=%s", vcdfile)) begin
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$dumpfile(vcdfile);
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$dumpvars(0, testbench);
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end
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end
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initial begin
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@(posedge ok);
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@(negedge ok);
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$display("ERROR: detected falling edge on OK pin!");
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$stop;
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end
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initial begin
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repeat (3000) @(posedge clk);
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if (!ok) begin
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$display("ERROR: OK pin not asserted after 3000 cycles!");
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$stop;
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end
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repeat (10000) @(posedge clk);
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$display("SUCCESS: OK pin still asserted after 10000 cycles.");
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$finish;
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end
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endmodule
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