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Merge pull request #107 from daveshah1/ultraplus_experiments 

Basic support for UltraPlus 5k
This commit is contained in:
Clifford Wolf 2017-11-14 19:08:47 +01:00 committed by GitHub
parent 3ba18d0017 c69b87d593
commit 539cf999dd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 1590 additions and 45 deletions
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35
icebox/icebox.py
View File

@ -1145,14 +1145,14 @@ extra_bits_db = {
(0, 331, 143): ("padin_glb_netwk", "7"),
},
"5k": {
(0, 690, 334): ("padin_glb_netwk", "0"), # (0 1) (690 334) (690 334) routing T_0_0.padin_0 <X> T_0_0.glb_netwk_0
(1, 691, 334): ("padin_glb_netwk", "1"), # (1 1) (691 334) (691 334) routing T_0_0.padin_1 <X> T_0_0.glb_netwk_1
(0, 690, 336): ("padin_glb_netwk", "2"), # (0 3) (690 336) (690 336) routing T_0_0.padin_2 <X> T_0_0.glb_netwk_2
(1, 871, 271): ("padin_glb_netwk", "3"),
(1, 870, 270): ("padin_glb_netwk", "4"),
(1, 871, 270): ("padin_glb_netwk", "5"),
(0, 870, 271): ("padin_glb_netwk", "6"),
(1, 691, 335): ("padin_glb_netwk", "7"), # (1 0) (691 335) (691 335) routing T_0_0.padin_7 <X> T_0_0.glb_netwk_7
(0, 690, 334): ("padin_glb_netwk", "0"), # check
(0, 691, 334): ("padin_glb_netwk", "1"), # good
(1, 690, 175): ("padin_glb_netwk", "2"), # good
(1, 691, 175): ("padin_glb_netwk", "3"), # check
(1, 690, 174): ("padin_glb_netwk", "4"), # good (INTOSC only)
(1, 691, 174): ("padin_glb_netwk", "5"), # good (INTOSC only)
(0, 690, 335): ("padin_glb_netwk", "6"), # check
(0, 691, 335): ("padin_glb_netwk", "7"), # good
},
"8k": {
(0, 870, 270): ("padin_glb_netwk", "0"),
@ -1190,8 +1190,8 @@ gbufin_db = {
"5k": [
( 6, 0, 6), #checked
(12, 0, 5), #checked
(13, 0, 7), #unknown
(19, 0, 0), #checked
(13, 0, 0), #checked
(19, 0, 7), #checked
( 6, 31, 3), #checked
(12, 31, 4), #checked
(13, 31, 1), #checked
@ -1677,11 +1677,16 @@ padin_pio_db = {
( 6, 17, 1), # glb_netwk_7
],
"5k": [
( 6, 0, 1),
(19, 0, 1),
( 6, 31, 0),
(12, 31, 1),
(13, 31, 0),
(19, 0, 1), #0 fixed
( 6, 0, 1), #1 fixed
(13, 31, 0), #2 fixed
(13, 0, 0), #3 fixed
(19, 31, 0), #These two are questionable, but keep the order correct
( 6, 31, 0), #They may need to be fixed if other package options are added.
(12, 0, 1), #6 fixed
(12, 31, 1), #7 fixed
],
"8k": [
(33, 16, 1),

90
icebox/iceboxdb.py
View File

@ -5372,19 +5372,32 @@ B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6
B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6
B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7
B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7
!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0
!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0
!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2
!B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2
!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4
!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4
!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6
!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6
!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4
!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5
!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6
!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7
!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK
!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1
!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2
!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3
!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK
B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK
!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE
B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0
B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1
B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2
B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3
B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK
!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0
!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1
!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2
!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3
@ -5396,11 +5409,15 @@ B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE
!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3
!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK
B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE
B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0
B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1
B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2
B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3
B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK
B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE
B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0
B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1
B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2
B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK
!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0
!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2
@ -5468,6 +5485,7 @@ B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1
B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3
B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5
B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7
B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5
B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7
B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11
B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13
@ -5494,6 +5512,7 @@ B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1
B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3
B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5
B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7
B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5
B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7
B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11
B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13
@ -5510,6 +5529,7 @@ B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_
!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5
!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7
!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11
!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13
!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15
!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9
B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11
@ -5534,7 +5554,9 @@ B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDAT
!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3
!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5
!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7
!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5
!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7
!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11
!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13
!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15
!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9
@ -5553,6 +5575,7 @@ B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA
!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8
!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE
B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10
B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12
B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14
B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8
B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1
@ -5608,6 +5631,7 @@ B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14
B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8
B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10
B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12
B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14
B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8
!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0
!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2
@ -5655,6 +5679,7 @@ B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE
!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3
!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5
!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7
!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5
!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7
!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11
!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13
@ -5711,6 +5736,7 @@ B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5
B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7
B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5
B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7
B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11
B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13
B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15
B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9
@ -5770,6 +5796,7 @@ B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_
!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14
!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8
B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE
B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10
B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12
B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14
B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8
@ -5805,6 +5832,7 @@ B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1
B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3
B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5
B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7
B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5
B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7
B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11
B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13
@ -5825,6 +5853,7 @@ B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14
B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8
B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10
B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12
B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14
B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8
B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0
B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0
@ -5904,6 +5933,7 @@ B6[2] buffer sp12_h_r_14 sp4_h_l_6
!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4
!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4
B12[2] buffer sp12_h_r_20 sp4_h_l_11
!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5
!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5
!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6
!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6
@ -5915,6 +5945,7 @@ B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7
!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0
!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0
B0[2] buffer sp12_h_r_8 sp4_h_r_16
!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1
!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1
B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0
B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0
@ -5990,6 +6021,7 @@ B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3
B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3
B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7
B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7
B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6
B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6
B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1
B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1
@ -6029,12 +6061,14 @@ B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1
B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1
!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4
!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4
B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5
B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5
!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3
!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3
!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7
!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7
B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0
B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0
B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1
B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1
B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2
@ -6067,6 +6101,7 @@ B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5
!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7
B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0
B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0
B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1
B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1
!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0
!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1
@ -6248,15 +6283,19 @@ B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1
!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2
!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3
!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3
!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4
!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4
B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5
B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5
!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6
!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6
!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7
!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7
B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1
B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17
B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10
B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15
B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10
B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42
B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11
B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27
@ -6268,6 +6307,7 @@ B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15
B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0
B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7
B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24
B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40
B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8
B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25
B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41
@ -6303,6 +6343,7 @@ B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9
B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18
B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1
B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18
B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2
B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34
B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19
B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3
@ -6327,7 +6368,9 @@ B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22
B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14
B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19
B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3
B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46
B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15
B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31
B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47
B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14
B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46
@ -6508,7 +6551,6 @@ B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45
!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5
!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40
B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46
!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39
!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43
B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44
B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11
@ -6524,7 +6566,6 @@ B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36
B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42
B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41
!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45
B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46
!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1
!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8
B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39
@ -6760,6 +6801,11 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7
!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6
!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7
!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK
!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1
!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2
!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3
!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK
B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK
B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0
B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1
@ -6770,6 +6816,7 @@ B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK
!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0
!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1
!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2
!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3
!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK
B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE
!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0
@ -6778,7 +6825,15 @@ B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE
!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3
!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK
B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE
B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0
B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1
B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2
B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3
B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK
B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE
B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0
B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2
B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3
B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK
!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0
!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2
@ -6820,6 +6875,7 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK
!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7
!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5
!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7
!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1
!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3
!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5
!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7
@ -6835,6 +6891,7 @@ B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6
B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0
B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2
B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4
B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6
!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0
!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2
!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4
@ -6861,6 +6918,7 @@ B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6
B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6
B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0
B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2
B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4
B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6
!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0
!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2
@ -6874,6 +6932,8 @@ B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5
B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7
B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1
B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3
B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5
B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7
!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1
!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3
!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5
@ -6914,6 +6974,8 @@ B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6
!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7
!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1
!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3
!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5
!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7
B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1
B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3
B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5
@ -6951,6 +7013,7 @@ B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2
B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4
B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6
B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6
B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0
B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2
B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4
B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6
@ -6965,6 +7028,8 @@ B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5
B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7
B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5
B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7
B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1
B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3
B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5
B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7
B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1
@ -6977,6 +7042,7 @@ B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4
B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6
B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6
B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0
B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2
B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4
B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6
B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0
@ -7187,6 +7253,7 @@ B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7
B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1
B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3
B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5
B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7
B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1
B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3
B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5
@ -7220,6 +7287,7 @@ B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6
B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6
B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7
B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7
B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0
B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0
B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1
B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1
@ -7237,10 +7305,12 @@ B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7
B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7
B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3
B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3
!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7
!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7
!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6
!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6
B6[2] buffer sp12_h_l_13 sp4_h_r_19
!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3
!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3
!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5
!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5
@ -7250,6 +7320,8 @@ B14[2] buffer sp12_h_l_21 sp4_h_l_10
B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4
B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4
B15[19] buffer sp12_h_l_3 sp4_h_l_3
B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7
B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7
B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6
B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6
B14[19] buffer sp12_h_l_5 sp4_h_l_2
@ -7263,11 +7335,14 @@ B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1
!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2
!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2
B3[1] buffer sp12_h_r_10 sp4_h_r_17
!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3
!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3
!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4
!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4
B4[2] buffer sp12_h_r_12 sp4_h_l_7
!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5
!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5
!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0
!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0
B8[2] buffer sp12_h_r_16 sp4_h_r_20
!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1
@ -7278,7 +7353,10 @@ B10[2] buffer sp12_h_r_18 sp4_h_l_8
B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2
B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2
B12[19] buffer sp12_h_r_2 sp4_h_r_13
!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4
!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4
B12[2] buffer sp12_h_r_20 sp4_h_r_22
!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7
!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7
B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5
B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5
@ -7364,6 +7442,7 @@ B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1
B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0
B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0
B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7
B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7
B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6
B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6
B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1
@ -7397,6 +7476,7 @@ B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1
B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3
B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3
!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2
!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2
B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4
B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4
B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6
@ -7627,8 +7707,11 @@ B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5
!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6
!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7
!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7
!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2
!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2
!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4
!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6
!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6
B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21
B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5
B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14
@ -7694,6 +7777,7 @@ B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19
B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3
B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20
B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36
B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4
B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21
B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37
B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5
@ -7770,7 +7854,6 @@ B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9
!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38
B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45
B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10
!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2
B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5
!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2
B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8
@ -7805,7 +7888,6 @@ B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6
!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43
B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46
B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0
!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5
!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9
B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3
B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9

648
icefuzz/cached_ramb_5k.txt
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File diff suppressed because it is too large Load Diff

595
icefuzz/cached_ramt_5k.txt
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File diff suppressed because it is too large Load Diff

51
icefuzz/tests/colbuf_5k.sh Executable file
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@ -0,0 +1,51 @@
#!/bin/bash
for f in colbuf_io_5k.work/*.exp colbuf_logic_5k.work/*.exp colbuf_ram_5k.work/*.exp; do
echo $f >&2
python3 colbuf.py $f
done | sort -u > colbuf_5k.txt
get_colbuf_data()
{
tr -d '(,)' < colbuf_5k.txt
# for x in {0..2} {4..9} {11..13}; do
# echo $x 4 $x 0
# echo $x 5 $x 8
# echo $x 12 $x 9
# echo $x 13 $x 17
# done
# for x in 3 10; do
# echo $x 3 $x 0
# echo $x 3 $x 4
# echo $x 5 $x 8
# echo $x 11 $x 9
# echo $x 11 $x 12
# echo $x 13 $x 17
# done
}
{
echo "<svg xmlns=\"http://www.w3.org/2000/svg\" height=\"1050\" width=\"1050\">"
for x in {1..33}; do
echo "<line x1=\"$((10+x*30))\" y1=\"10\" x2=\"$((10+x*30))\" y2=\"$((10+34*30))\" style=\"stroke:rgb(0,0,0);stroke-width:3\" />"
done
for y in {1..33}; do
echo "<line x1=\"10\" y1=\"$((10+y*30))\" x2=\"$((10+34*30))\" y2=\"$((10+y*30))\" style=\"stroke:rgb(0,0,0);stroke-width:3\" />"
done
for x in {0..33}; do
echo "<text x=\"$((10+$x*30+7))\" y=\"$((10+34*30+15))\" fill=\"black\">$x</text>"
done
for y in {0..33}; do
echo "<text x=\"$((10+34*30+5))\" y=\"$((10+(33-y)*30+20))\" fill=\"black\">$y</text>"
done
while read x1 y1 x2 y2; do
echo "<line x1=\"$((10+x1*30+15))\" y1=\"$((10+(33-y1)*30+15))\" x2=\"$((10+x2*30+15))\" y2=\"$((10+(33-y2)*30+15))\" style=\"stroke:rgb(255,0,0);stroke-width:5\" />"
done < <( get_colbuf_data; )
while read x1 y1 x2 y2; do
echo "<circle cx=\"$((10+x2*30+15))\" cy=\"$((10+(33-y2)*30+15))\" r=\"4\" fill=\"blue\" />"
done < <( get_colbuf_data; )
while read x1 y1 x2 y2; do
echo "<circle cx=\"$((10+x1*30+15))\" cy=\"$((10+(33-y1)*30+15))\" r=\"5\" fill=\"gray\" />"
done < <( get_colbuf_data; )
echo "</svg>"
} > colbuf_8k.svg

37
icefuzz/tests/colbuf_io_5k.sh Executable file
View File

@ -0,0 +1,37 @@
#!/bin/bash
set -ex
mkdir -p colbuf_io_5k.work
cd colbuf_io_5k.work
glb_pins="20 35 37 44"
pins="
2 3 4 6 9 10 11 12
13 18 19 20 21
25 26 27 28 31 32 34 35 36
37 38 42 43 44 45 46 47 48
"
pins="$( echo $pins )"
for pin in $pins; do
pf="colbuf_io_5k_$pin"
gpin=$( echo $glb_pins | tr ' ' '\n' | grep -v $pin | sort -R | head -n1; )
cat > ${pf}.v <<- EOT
module top (input clk, data, output pin);
SB_IO #(
.PIN_TYPE(6'b 0101_00)
) pin_obuf (
.PACKAGE_PIN(pin),
.OUTPUT_CLK(clk),
.D_OUT_0(data)
);
endmodule
EOT
echo "set_io pin $pin" > ${pf}.pcf
echo "set_io clk $gpin" >> ${pf}.pcf
ICEDEV=up5k-sg48 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp
rm -rf ${pf}.tmp
done

28
icefuzz/tests/colbuf_logic_5k.sh Executable file
View File

@ -0,0 +1,28 @@
#!/bin/bash
set -ex
mkdir -p colbuf_logic_5k.work
cd colbuf_logic_5k.work
glb_pins="20 35 37 44"
for x in {1..5} {7..18} {20..24}; do
for y in {1..30}; do
pf="colbuf_logic_5k_${x}_${y}"
gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; )
cat > ${pf}.v <<- EOT
module top (input c, d, output q);
SB_DFF dff (
.C(c),
.D(d),
.Q(q)
);
endmodule
EOT
echo "set_location dff $x $y 0" > ${pf}.pcf
echo "set_io c $gpin" >> ${pf}.pcf
ICEDEV=up5k-sg48 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp
rm -rf ${pf}.tmp
done; done

56
icefuzz/tests/colbuf_ram_5k.sh Executable file
View File

@ -0,0 +1,56 @@
#!/bin/bash
set -ex
mkdir -p colbuf_ram_5k.work
cd colbuf_ram_5k.work
glb_pins="20 35 37 44"
for x in 6 19; do
for y in {1..30}; do
pf="colbuf_ram_5k_${x}_${y}"
gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; )
if [ $((y % 2)) == 1 ]; then
clkport="WCLK"
other_clkport="RCLK"
else
clkport="RCLK"
other_clkport="WCLK"
fi
cat > ${pf}.v <<- EOT
module top (input c, oc, input [1:0] d, output [1:0] q);
wire gc;
SB_GB_IO #(
.PIN_TYPE(6'b 0000_00),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS")
) gbuf (
.PACKAGE_PIN(c),
.GLOBAL_BUFFER_OUTPUT(gc)
);
SB_RAM40_4K #(
.READ_MODE(3),
.WRITE_MODE(3)
) ram40 (
.WADDR(11'b0),
.RADDR(11'b0),
.$clkport(gc),
.$other_clkport(oc),
.RDATA(q),
.WDATA(d),
.WE(1'b1),
.WCLKE(1'b1),
.RE(1'b1),
.RCLKE(1'b1)
);
endmodule
EOT
echo "set_location ram40 $x $((y - (1 - y%2))) 0" > ${pf}.pcf
echo "set_io oc 1" >> ${pf}.pcf
echo "set_io c $gpin" >> ${pf}.pcf
ICEDEV=up5k-sg48 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp
rm -rf ${pf}.tmp
done; done

95
icepack/icepack.cc
View File

@ -451,11 +451,12 @@ void FpgaConfig::write_bits(std::ostream &ofs) const
write_byte(ofs, crc_value, file_offset, 0x62);
write_byte(ofs, crc_value, file_offset, (this->cram_width-1) >> 8);
write_byte(ofs, crc_value, file_offset, (this->cram_width-1));
debug("CRAM: Setting bank height to %d.\n", this->cram_height);
write_byte(ofs, crc_value, file_offset, 0x72);
write_byte(ofs, crc_value, file_offset, this->cram_height >> 8);
write_byte(ofs, crc_value, file_offset, this->cram_height);
if(this->device != "5k") {
debug("CRAM: Setting bank height to %d.\n", this->cram_height);
write_byte(ofs, crc_value, file_offset, 0x72);
write_byte(ofs, crc_value, file_offset, this->cram_height >> 8);
write_byte(ofs, crc_value, file_offset, this->cram_height);
}
debug("CRAM: Setting bank offset to 0.\n");
write_byte(ofs, crc_value, file_offset, 0x82);
@ -465,10 +466,20 @@ void FpgaConfig::write_bits(std::ostream &ofs) const
for (int cram_bank = 0; cram_bank < 4; cram_bank++)
{
vector<bool> cram_bits;
for (int cram_y = 0; cram_y < this->cram_height; cram_y++)
int height = this->cram_height;
if(this->device == "5k" && ((cram_bank % 2) == 1))
height = height / 2 + 8;
for (int cram_y = 0; cram_y < height; cram_y++)
for (int cram_x = 0; cram_x < this->cram_width; cram_x++)
cram_bits.push_back(this->cram[cram_bank][cram_x][cram_y]);
if(this->device == "5k") {
debug("CRAM: Setting bank height to %d.\n", height);
write_byte(ofs, crc_value, file_offset, 0x72);
write_byte(ofs, crc_value, file_offset, height >> 8);
write_byte(ofs, crc_value, file_offset, height);
}
debug("CRAM: Setting bank %d.\n", cram_bank);
write_byte(ofs, crc_value, file_offset, 0x11);
write_byte(ofs, crc_value, file_offset, cram_bank);
@ -491,10 +502,13 @@ void FpgaConfig::write_bits(std::ostream &ofs) const
if (this->bram_width && this->bram_height)
{
debug("BRAM: Setting bank width to %d.\n", this->bram_width);
write_byte(ofs, crc_value, file_offset, 0x62);
write_byte(ofs, crc_value, file_offset, (this->bram_width-1) >> 8);
write_byte(ofs, crc_value, file_offset, (this->bram_width-1));
if(this->device != "5k") {
debug("BRAM: Setting bank width to %d.\n", this->bram_width);
write_byte(ofs, crc_value, file_offset, 0x62);
write_byte(ofs, crc_value, file_offset, (this->bram_width-1) >> 8);
write_byte(ofs, crc_value, file_offset, (this->bram_width-1));
}
debug("BRAM: Setting bank height to %d.\n", this->bram_height);
write_byte(ofs, crc_value, file_offset, 0x72);
@ -510,8 +524,11 @@ void FpgaConfig::write_bits(std::ostream &ofs) const
for (int offset = 0; offset < this->bram_height; offset += bram_chunk_size)
{
vector<bool> bram_bits;
int width = this->bram_width;
if(this->device == "5k" && ((bram_bank % 2) == 1))
width = width / 2;
for (int bram_y = 0; bram_y < bram_chunk_size; bram_y++)
for (int bram_x = 0; bram_x < this->bram_width; bram_x++)
for (int bram_x = 0; bram_x < width; bram_x++)
bram_bits.push_back(this->bram[bram_bank][bram_x][bram_y+offset]);
debug("BRAM: Setting bank offset to %d.\n", offset);
@ -519,6 +536,14 @@ void FpgaConfig::write_bits(std::ostream &ofs) const
write_byte(ofs, crc_value, file_offset, offset >> 8);
write_byte(ofs, crc_value, file_offset, offset);
if(this->device == "5k") {
debug("BRAM: Setting bank width to %d.\n", width);
write_byte(ofs, crc_value, file_offset, 0x62);
write_byte(ofs, crc_value, file_offset, (width-1) >> 8);
write_byte(ofs, crc_value, file_offset, (width-1));
}
debug("BRAM: Writing bank %d data.\n", bram_bank);
write_byte(ofs, crc_value, file_offset, 0x01);
write_byte(ofs, crc_value, file_offset, 0x03);
@ -632,18 +657,35 @@ void FpgaConfig::read_ascii(std::istream &ifs)
error("Unsupported chip type '%s'.\n", this->device.c_str());
this->cram.resize(4);
for (int i = 0; i < 4; i++) {
this->cram[i].resize(this->cram_width);
for (int x = 0; x < this->cram_width; x++)
this->cram[i][x].resize(this->cram_height);
if(this->device == "5k") {
for (int i = 0; i < 4; i++) {
this->cram[i].resize(this->cram_width);
for (int x = 0; x < this->cram_width; x++)
this->cram[i][x].resize(((i % 2) == 1) ? (this->cram_height / 2 + 8) : this->cram_height);
}
this->bram.resize(4);
for (int i = 0; i < 4; i++) {
int width = ((i % 2) == 1) ? (this->bram_width / 2) : this->bram_width;
this->bram[i].resize(width);
for (int x = 0; x < width; x++)
this->bram[i][x].resize(this->bram_height);
}
} else {
for (int i = 0; i < 4; i++) {
this->cram[i].resize(this->cram_width);
for (int x = 0; x < this->cram_width; x++)
this->cram[i][x].resize(this->cram_height);
}
this->bram.resize(4);
for (int i = 0; i < 4; i++) {
this->bram[i].resize(this->bram_width);
for (int x = 0; x < this->bram_width; x++)
this->bram[i][x].resize(this->bram_height);
}
}
this->bram.resize(4);
for (int i = 0; i < 4; i++) {
this->bram[i].resize(this->bram_width);
for (int x = 0; x < this->bram_width; x++)
this->bram[i][x].resize(this->bram_height);
}
got_device = true;
continue;
@ -661,7 +703,7 @@ void FpgaConfig::read_ascii(std::istream &ifs)
continue;
}
if (command == ".io_tile" || command == ".logic_tile" || command == ".ramb_tile" || command == ".ramt_tile")
if (command == ".io_tile" || command == ".logic_tile" || command == ".ramb_tile" || command == ".ramt_tile" || command.substr(0, 4) == ".dsp" || command == ".ipconn_tile")
{
if (!got_device)
error("Missing .device statement before %s.\n", command.c_str());
@ -1165,16 +1207,17 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
// used for SRAM instead of logic. Therefore the bitstream for the top two
// quadrants are half the height of the bottom.
if (this->fpga->device == "5k") {
top_half = this->tile_y > (chip_height / 3);
top_half = this->tile_y > (2 * chip_height / 3);
}
this->bank_num = 0;
int y_offset = this->tile_y - 1;
if (this->fpga->device == "5k") {
if (!top_half) {
if (top_half) {
this->bank_num |= 1;
y_offset = this->tile_y - (2 * chip_height / 3);
} else {
y_offset = this->tile_y - (chip_height / 3);
//y_offset = this->tile_y - (2 * chip_height / 3);
}
} else if (top_half) {
this->bank_num |= 1;