mirror of https://github.com/YosysHQ/icestorm.git
Merge branch 'hermitsoft'
This commit is contained in:
Clifford Wolf
commit
4a4be48c34
|
|
@ -1,3 +1,4 @@
|
|||
chipdb-1k.txt
|
||||
chipdb-8k.txt
|
||||
chipdb-384.txt
|
||||
__pycache__
|
||||
|
|
|
|||
|
|
@ -1,6 +1,10 @@
|
|||
include ../config.mk
|
||||
|
||||
all: chipdb-1k.txt chipdb-8k.txt
|
||||
all: chipdb-1k.txt chipdb-8k.txt # chipdb-384.txt
|
||||
|
||||
chipdb-384.txt: icebox.py iceboxdb.py icebox_chipdb.py
|
||||
python3 icebox_chipdb.py -3 > chipdb-384.new
|
||||
mv chipdb-384.new chipdb-384.txt
|
||||
|
||||
chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py
|
||||
python3 icebox_chipdb.py > chipdb-1k.new
|
||||
|
|
@ -11,12 +15,13 @@ chipdb-8k.txt: icebox.py iceboxdb.py icebox_chipdb.py
|
|||
mv chipdb-8k.new chipdb-8k.txt
|
||||
|
||||
clean:
|
||||
rm -f chipdb-1k.txt chipdb-8k.txt
|
||||
rm -f chipdb-1k.txt chipdb-8k.txt chipdb-384.txt
|
||||
rm -f icebox.pyc iceboxdb.pyc
|
||||
|
||||
install: all
|
||||
mkdir -p $(DESTDIR)$(PREFIX)/share/icebox
|
||||
mkdir -p $(DESTDIR)$(PREFIX)/bin
|
||||
cp chipdb-384.txt $(DESTDIR)$(PREFIX)/share/icebox/
|
||||
cp chipdb-1k.txt $(DESTDIR)$(PREFIX)/share/icebox/
|
||||
cp chipdb-8k.txt $(DESTDIR)$(PREFIX)/share/icebox/
|
||||
cp icebox.py $(DESTDIR)$(PREFIX)/bin/icebox.py
|
||||
|
|
@ -41,6 +46,7 @@ uninstall:
|
|||
rm -f $(DESTDIR)$(PREFIX)/bin/icebox_maps
|
||||
rm -f $(DESTDIR)$(PREFIX)/bin/icebox_vlog
|
||||
rm -f $(DESTDIR)$(PREFIX)/bin/icebox_stat
|
||||
rm -f $(DESTDIR)$(PREFIX)/share/icebox/chipdb-384.txt
|
||||
rm -f $(DESTDIR)$(PREFIX)/share/icebox/chipdb-1k.txt
|
||||
rm -f $(DESTDIR)$(PREFIX)/share/icebox/chipdb-8k.txt
|
||||
-rmdir $(DESTDIR)$(PREFIX)/share/icebox
|
||||
|
|
|
|||
|
|
@ -34,6 +34,24 @@ class iceconfig:
|
|||
self.extra_bits = set()
|
||||
self.symbols = dict()
|
||||
|
||||
def setup_empty_384(self):
|
||||
self.clear()
|
||||
self.device = "384"
|
||||
self.max_x = 7
|
||||
self.max_y = 9
|
||||
|
||||
for x in range(1, self.max_x):
|
||||
for y in range(1, self.max_y):
|
||||
self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)]
|
||||
|
||||
for x in range(1, self.max_x):
|
||||
self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)]
|
||||
self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)]
|
||||
|
||||
for y in range(1, self.max_y):
|
||||
self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)]
|
||||
self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)]
|
||||
|
||||
def setup_empty_1k(self):
|
||||
self.clear()
|
||||
self.device = "1k"
|
||||
|
|
@ -96,6 +114,7 @@ class iceconfig:
|
|||
return None
|
||||
|
||||
def pinloc_db(self):
|
||||
if self.device == "384": return pinloc_db["384-qn32"]
|
||||
if self.device == "1k": return pinloc_db["1k-tq144"]
|
||||
if self.device == "8k": return pinloc_db["8k-ct256"]
|
||||
assert False
|
||||
|
|
@ -120,6 +139,8 @@ class iceconfig:
|
|||
return ["1k"]
|
||||
if self.device == "8k":
|
||||
return ["8k_0", "8k_1"]
|
||||
if self.device == "384":
|
||||
return [ ]
|
||||
assert False
|
||||
|
||||
def colbuf_db(self):
|
||||
|
|
@ -148,7 +169,7 @@ class iceconfig:
|
|||
if 25 <= y <= 33: src_y = 25
|
||||
entries.append((x, src_y, x, y))
|
||||
return entries
|
||||
|
||||
#384?
|
||||
assert False
|
||||
|
||||
def tile_db(self, x, y):
|
||||
|
|
@ -164,6 +185,8 @@ class iceconfig:
|
|||
if (x, y) in self.logic_tiles: return logictile_8k_db
|
||||
if (x, y) in self.ramb_tiles: return rambtile_8k_db
|
||||
if (x, y) in self.ramt_tiles: return ramttile_8k_db
|
||||
if self.device == "384":
|
||||
if (x, y) in self.logic_tiles: return logictile_384_db
|
||||
assert False
|
||||
|
||||
def tile_type(self, x, y):
|
||||
|
|
@ -441,6 +464,8 @@ class iceconfig:
|
|||
add_seed_segments(idx, tile, logictile_db)
|
||||
elif self.device == "8k":
|
||||
add_seed_segments(idx, tile, logictile_8k_db)
|
||||
elif self.device == "384":
|
||||
add_seed_segments(idx, tile, logictile_384_db)
|
||||
else:
|
||||
assert False
|
||||
|
||||
|
|
@ -574,7 +599,7 @@ class iceconfig:
|
|||
self.extra_bits.add((int(line[1]), int(line[2]), int(line[3])))
|
||||
continue
|
||||
if line[0] == ".device":
|
||||
assert line[1] in ["1k", "8k"]
|
||||
assert line[1] in ["1k", "8k", "384"]
|
||||
self.device = line[1]
|
||||
continue
|
||||
if line[0] == ".sym":
|
||||
|
|
@ -948,6 +973,7 @@ def run_checks_neigh():
|
|||
ic = iceconfig()
|
||||
ic.setup_empty_1k()
|
||||
# ic.setup_empty_8k()
|
||||
# ic.setup_empty_384()
|
||||
|
||||
all_segments = set()
|
||||
|
||||
|
|
@ -983,19 +1009,26 @@ def run_checks_neigh():
|
|||
def run_checks():
|
||||
run_checks_neigh()
|
||||
|
||||
def parse_db(text, grep_8k=False):
|
||||
def parse_db(text, grep_8k=False, grep_384=False):
|
||||
db = list()
|
||||
for line in text.split("\n"):
|
||||
line_384 = line.replace("384_glb_netwk_", "glb_netwk_")
|
||||
line_1k = line.replace("1k_glb_netwk_", "glb_netwk_")
|
||||
line_8k = line.replace("8k_glb_netwk_", "glb_netwk_")
|
||||
if line_1k != line:
|
||||
if grep_8k:
|
||||
continue
|
||||
if grep_384:
|
||||
continue
|
||||
line = line_1k
|
||||
elif line_8k != line:
|
||||
if not grep_8k:
|
||||
continue
|
||||
line = line_8k
|
||||
elif line_384 != line:
|
||||
if not grep_384:
|
||||
continue
|
||||
line = line_384
|
||||
line = line.split("\t")
|
||||
if len(line) == 0 or line[0] == "":
|
||||
continue
|
||||
|
|
@ -1024,6 +1057,7 @@ extra_bits_db = {
|
|||
(0, 870, 271): ("padin_glb_netwk", "6"),
|
||||
(0, 871, 271): ("padin_glb_netwk", "7"),
|
||||
}
|
||||
#384?
|
||||
}
|
||||
|
||||
gbufin_db = {
|
||||
|
|
@ -1047,6 +1081,7 @@ gbufin_db = {
|
|||
(16, 0, 5),
|
||||
(16, 33, 4),
|
||||
]
|
||||
#384?
|
||||
}
|
||||
|
||||
iolatch_db = {
|
||||
|
|
@ -1062,6 +1097,7 @@ iolatch_db = {
|
|||
(18, 0),
|
||||
(15, 33),
|
||||
],
|
||||
#384?
|
||||
}
|
||||
|
||||
warmbootinfo_db = {
|
||||
|
|
@ -1075,6 +1111,7 @@ warmbootinfo_db = {
|
|||
"S0": ( 33, 1, "fabout" ),
|
||||
"S1": ( 33, 2, "fabout" ),
|
||||
}
|
||||
#384?
|
||||
}
|
||||
|
||||
noplls_db = {
|
||||
|
|
@ -1087,6 +1124,7 @@ noplls_db = {
|
|||
"1k-cb81": [ "1k" ],
|
||||
"1k-cb121": [ "1k" ],
|
||||
"1k-vq100": [ "1k" ],
|
||||
"384-qn32": [ "384" ],
|
||||
}
|
||||
|
||||
pllinfo_db = {
|
||||
|
|
@ -1369,6 +1407,7 @@ pllinfo_db = {
|
|||
"SDI": ( 22, 33, "fabout"),
|
||||
"SCLK": ( 21, 33, "fabout"),
|
||||
},
|
||||
#384?
|
||||
}
|
||||
|
||||
padin_pio_db = {
|
||||
|
|
@ -1392,6 +1431,7 @@ padin_pio_db = {
|
|||
(16, 0, 1),
|
||||
(16, 33, 1),
|
||||
]
|
||||
#384?
|
||||
}
|
||||
|
||||
ieren_db = {
|
||||
|
|
@ -1719,6 +1759,7 @@ ieren_db = {
|
|||
(33, 30, 1, 33, 30, 1),
|
||||
(33, 31, 0, 33, 31, 0),
|
||||
]
|
||||
#384?
|
||||
}
|
||||
|
||||
pinloc_db = {
|
||||
|
|
@ -3636,11 +3677,13 @@ pinloc_db = {
|
|||
("T15", 22, 0, 1),
|
||||
("T16", 27, 0, 0),
|
||||
]
|
||||
#384?
|
||||
}
|
||||
|
||||
iotile_full_db = parse_db(iceboxdb.database_io_txt)
|
||||
logictile_db = parse_db(iceboxdb.database_logic_txt)
|
||||
logictile_8k_db = parse_db(iceboxdb.database_logic_txt, True)
|
||||
logictile_384_db = parse_db(iceboxdb.database_logic_txt, False, True)
|
||||
rambtile_db = parse_db(iceboxdb.database_ramb_txt)
|
||||
ramttile_db = parse_db(iceboxdb.database_ramt_txt)
|
||||
rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, True)
|
||||
|
|
@ -3680,6 +3723,8 @@ logictile_db.append([["B1[50]"], "CarryInSet"])
|
|||
logictile_8k_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"])
|
||||
logictile_8k_db.append([["B1[50]"], "CarryInSet"])
|
||||
|
||||
#384?
|
||||
|
||||
for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, logictile_8k_db, rambtile_db, ramttile_db, rambtile_8k_db, ramttile_8k_db]:
|
||||
for entry in db:
|
||||
if entry[1] in ("buffer", "routing"):
|
||||
|
|
|
|||
|
|
@ -18,31 +18,39 @@
|
|||
import icebox
|
||||
import getopt, sys, re
|
||||
|
||||
mode_384 = False
|
||||
mode_8k = False
|
||||
|
||||
def usage():
|
||||
print("""
|
||||
Usage: icebox_chipdb [options] [bitmap.asc]
|
||||
|
||||
-3
|
||||
create chipdb for 384 device
|
||||
|
||||
-8
|
||||
create chipdb for 8k device
|
||||
""")
|
||||
sys.exit(0)
|
||||
|
||||
try:
|
||||
opts, args = getopt.getopt(sys.argv[1:], "8")
|
||||
opts, args = getopt.getopt(sys.argv[1:], "38")
|
||||
except:
|
||||
usage()
|
||||
|
||||
for o, a in opts:
|
||||
if o == "-8":
|
||||
mode_8k = True
|
||||
elif o == "-3":
|
||||
mode_384 = True
|
||||
else:
|
||||
usage()
|
||||
|
||||
ic = icebox.iceconfig()
|
||||
if mode_8k:
|
||||
ic.setup_empty_8k()
|
||||
elif mode_384:
|
||||
ic.setup_empty_384()
|
||||
else:
|
||||
ic.setup_empty_1k()
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,9 @@ include ../config.mk
|
|||
export LC_ALL=C
|
||||
export ICE_SBTIMER_LP=1
|
||||
|
||||
#EIGTHK = _8k
|
||||
THREEH = _384
|
||||
|
||||
TESTS =
|
||||
TESTS += binop
|
||||
TESTS += pin2pin
|
||||
|
|
@ -15,12 +18,12 @@ TESTS += gbio
|
|||
TESTS += gbio2
|
||||
TESTS += prim
|
||||
TESTS += fflogic
|
||||
TESTS += ram40
|
||||
TESTS += mem
|
||||
TESTS += pll
|
||||
TESTS += aig
|
||||
|
||||
EIGTHK = _8k
|
||||
ifneq ($(THREEH),_384)
|
||||
TESTS += ram40
|
||||
TESTS += mem
|
||||
TESTS += pll
|
||||
TESTS += aig
|
||||
endif
|
||||
|
||||
database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(EIGTHK).txt bitdata_ramt$(EIGTHK).txt
|
||||
ifeq ($(EIGTHK),_8k)
|
||||
|
|
@ -49,6 +52,13 @@ ifeq ($(EIGTHK),_8k)
|
|||
python3 timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new
|
||||
mv timings_lp8k.new timings_lp8k.txt
|
||||
else
|
||||
ifeq ($(THREEH),_384)
|
||||
cp tmedges.txt tmedges.tmp
|
||||
set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
|
||||
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
|
||||
python3 timings.py -t timings_lp384.txt work_*/*.slp > timings_lp384.new
|
||||
mv timings_lp384.new timings_lp384.txt
|
||||
else
|
||||
cp tmedges.txt tmedges.tmp
|
||||
set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
|
||||
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
|
||||
|
|
@ -56,6 +66,7 @@ else
|
|||
mv timings_hx1k.new timings_hx1k.txt
|
||||
python3 timings.py -t timings_lp1k.txt work_*/*.slp > timings_lp1k.new
|
||||
mv timings_lp1k.new timings_lp1k.txt
|
||||
endif
|
||||
endif
|
||||
|
||||
timings_html:
|
||||
|
|
@ -63,6 +74,7 @@ timings_html:
|
|||
python3 timings.py -h tmedges.txt -t timings_hx8k.txt -l "HX8K with default temp/volt settings" > timings_hx8k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_lp1k.txt -l "LP1K with default temp/volt settings" > timings_lp1k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html
|
||||
|
||||
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt
|
||||
gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
|
||||
|
|
@ -95,9 +107,15 @@ ifeq ($(EIGTHK),_8k)
|
|||
+ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1)
|
||||
python3 extract.py -8 work_$(1)/*.glb > $$@
|
||||
else
|
||||
ifeq ($(THREEH),_384)
|
||||
ICE384PINS=1 python3 make_$(1).py
|
||||
+ICEDEV=lp384-qn32 $(MAKE) -C work_$(1)
|
||||
python3 extract.py -3 work_$(1)/*.glb > $$@
|
||||
else
|
||||
python3 make_$(1).py
|
||||
+$(MAKE) -C work_$(1)
|
||||
python3 extract.py work_$(1)/*.glb > $$@
|
||||
endif
|
||||
endif
|
||||
endef
|
||||
|
||||
|
|
|
|||
|
|
@ -527,19 +527,27 @@
|
|||
(2 6) IO control bit: BIODOWN_REN_0
|
||||
(2 6) IO control bit: BIOLEFT_REN_0
|
||||
(2 6) IO control bit: BIORIGHT_REN_0
|
||||
(2 6) IO control bit: BIORIGHT_REN_1
|
||||
(2 6) IO control bit: BIOUP_REN_0
|
||||
(2 6) IO control bit: GIODOWN0_REN_0
|
||||
(2 6) IO control bit: GIODOWN1_REN_0
|
||||
(2 6) IO control bit: GIOLEFT0_REN_0
|
||||
(2 6) IO control bit: GIOLEFT0_REN_1
|
||||
(2 6) IO control bit: GIOLEFT1_REN_0
|
||||
(2 6) IO control bit: GIOLEFT1_REN_1
|
||||
(2 6) IO control bit: GIORIGHT0_REN_0
|
||||
(2 6) IO control bit: GIORIGHT1_REN_0
|
||||
(2 6) IO control bit: GIORIGHT1_REN_1
|
||||
(2 6) IO control bit: GIOUP0_REN_0
|
||||
(2 6) IO control bit: GIOUP1_REN_0
|
||||
(2 6) IO control bit: GIOUP1_REN_1
|
||||
(2 6) IO control bit: IODOWN_REN_0
|
||||
(2 6) IO control bit: IODOWN_REN_1
|
||||
(2 6) IO control bit: IOLEFT_REN_0
|
||||
(2 6) IO control bit: IOLEFT_REN_1
|
||||
(2 6) IO control bit: IORIGHT_REN_0
|
||||
(2 6) IO control bit: IOUP_REN_0
|
||||
(2 6) IO control bit: IOUP_REN_1
|
||||
(2 7) Enable bit of Mux _out_links/OutMux9_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_13
|
||||
(2 7) Enable bit of Mux _out_links/OutMux9_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_13
|
||||
(2 8) IO control bit: BIOLEFT_LVDS_en
|
||||
|
|
@ -557,19 +565,29 @@
|
|||
(3 0) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_2
|
||||
(3 1) IO control bit: BIODOWN_REN_1
|
||||
(3 1) IO control bit: BIOLEFT_REN_1
|
||||
(3 1) IO control bit: BIORIGHT_REN_0
|
||||
(3 1) IO control bit: BIORIGHT_REN_1
|
||||
(3 1) IO control bit: BIOUP_REN_0
|
||||
(3 1) IO control bit: BIOUP_REN_1
|
||||
(3 1) IO control bit: GIODOWN0_REN_1
|
||||
(3 1) IO control bit: GIODOWN1_REN_1
|
||||
(3 1) IO control bit: GIOLEFT0_REN_0
|
||||
(3 1) IO control bit: GIOLEFT0_REN_1
|
||||
(3 1) IO control bit: GIOLEFT1_REN_0
|
||||
(3 1) IO control bit: GIOLEFT1_REN_1
|
||||
(3 1) IO control bit: GIORIGHT0_REN_0
|
||||
(3 1) IO control bit: GIORIGHT0_REN_1
|
||||
(3 1) IO control bit: GIORIGHT1_REN_0
|
||||
(3 1) IO control bit: GIORIGHT1_REN_1
|
||||
(3 1) IO control bit: GIOUP0_REN_0
|
||||
(3 1) IO control bit: GIOUP0_REN_1
|
||||
(3 1) IO control bit: GIOUP1_REN_1
|
||||
(3 1) IO control bit: IODOWN_REN_0
|
||||
(3 1) IO control bit: IODOWN_REN_1
|
||||
(3 1) IO control bit: IOLEFT_REN_0
|
||||
(3 1) IO control bit: IOLEFT_REN_1
|
||||
(3 1) IO control bit: IORIGHT_REN_1
|
||||
(3 1) IO control bit: IOUP_REN_0
|
||||
(3 1) IO control bit: IOUP_REN_1
|
||||
(3 11) Icegate Enable bit: GIODOWN0_padin_latch_enable
|
||||
(3 11) Icegate Enable bit: GIODOWN1_padin_latch_enable
|
||||
|
|
@ -616,19 +634,29 @@
|
|||
(3 5) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_6
|
||||
(3 6) IO control bit: BIODOWN_IE_1
|
||||
(3 6) IO control bit: BIOLEFT_IE_1
|
||||
(3 6) IO control bit: BIORIGHT_IE_0
|
||||
(3 6) IO control bit: BIORIGHT_IE_1
|
||||
(3 6) IO control bit: BIOUP_IE_0
|
||||
(3 6) IO control bit: BIOUP_IE_1
|
||||
(3 6) IO control bit: GIODOWN0_IE_1
|
||||
(3 6) IO control bit: GIODOWN1_IE_1
|
||||
(3 6) IO control bit: GIOLEFT0_IE_0
|
||||
(3 6) IO control bit: GIOLEFT0_IE_1
|
||||
(3 6) IO control bit: GIOLEFT1_IE_0
|
||||
(3 6) IO control bit: GIOLEFT1_IE_1
|
||||
(3 6) IO control bit: GIORIGHT0_IE_0
|
||||
(3 6) IO control bit: GIORIGHT0_IE_1
|
||||
(3 6) IO control bit: GIORIGHT1_IE_0
|
||||
(3 6) IO control bit: GIORIGHT1_IE_1
|
||||
(3 6) IO control bit: GIOUP0_IE_0
|
||||
(3 6) IO control bit: GIOUP0_IE_1
|
||||
(3 6) IO control bit: GIOUP1_IE_1
|
||||
(3 6) IO control bit: IODOWN_IE_0
|
||||
(3 6) IO control bit: IODOWN_IE_1
|
||||
(3 6) IO control bit: IOLEFT_IE_0
|
||||
(3 6) IO control bit: IOLEFT_IE_1
|
||||
(3 6) IO control bit: IORIGHT_IE_1
|
||||
(3 6) IO control bit: IOUP_IE_0
|
||||
(3 6) IO control bit: IOUP_IE_1
|
||||
(3 7) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_9
|
||||
(3 7) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_9
|
||||
|
|
@ -641,19 +669,27 @@
|
|||
(3 9) IO control bit: BIODOWN_IE_0
|
||||
(3 9) IO control bit: BIOLEFT_IE_0
|
||||
(3 9) IO control bit: BIORIGHT_IE_0
|
||||
(3 9) IO control bit: BIORIGHT_IE_1
|
||||
(3 9) IO control bit: BIOUP_IE_0
|
||||
(3 9) IO control bit: GIODOWN0_IE_0
|
||||
(3 9) IO control bit: GIODOWN1_IE_0
|
||||
(3 9) IO control bit: GIOLEFT0_IE_0
|
||||
(3 9) IO control bit: GIOLEFT0_IE_1
|
||||
(3 9) IO control bit: GIOLEFT1_IE_0
|
||||
(3 9) IO control bit: GIOLEFT1_IE_1
|
||||
(3 9) IO control bit: GIORIGHT0_IE_0
|
||||
(3 9) IO control bit: GIORIGHT1_IE_0
|
||||
(3 9) IO control bit: GIORIGHT1_IE_1
|
||||
(3 9) IO control bit: GIOUP0_IE_0
|
||||
(3 9) IO control bit: GIOUP1_IE_0
|
||||
(3 9) IO control bit: GIOUP1_IE_1
|
||||
(3 9) IO control bit: IODOWN_IE_0
|
||||
(3 9) IO control bit: IODOWN_IE_1
|
||||
(3 9) IO control bit: IOLEFT_IE_0
|
||||
(3 9) IO control bit: IOLEFT_IE_1
|
||||
(3 9) IO control bit: IORIGHT_IE_0
|
||||
(3 9) IO control bit: IOUP_IE_0
|
||||
(3 9) IO control bit: IOUP_IE_1
|
||||
(4 0) routing IO_B.logic_op_tnl_0 <X> lc_trk_g0_0
|
||||
(4 0) routing IO_B.logic_op_top_0 <X> lc_trk_g0_0
|
||||
(4 0) routing IO_L.logic_op_rgt_0 <X> lc_trk_g0_0
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ import sys, re
|
|||
db = set()
|
||||
text_db = dict()
|
||||
mode_8k = False
|
||||
mode_384 = False
|
||||
cur_text_db = None
|
||||
max_x, max_y = 0, 0
|
||||
|
||||
|
|
@ -12,6 +13,10 @@ if sys.argv[1] == '-8':
|
|||
sys.argv = sys.argv[1:]
|
||||
mode_8k = True
|
||||
|
||||
if sys.argv[1] == '-3':
|
||||
sys.argv = sys.argv[1:]
|
||||
mode_384 = True
|
||||
|
||||
for filename in sys.argv[1:]:
|
||||
with open(filename, "r") as f:
|
||||
for line in f:
|
||||
|
|
|
|||
|
|
@ -26,6 +26,18 @@ if os.getenv('ICE8KPINS'):
|
|||
|
||||
gpins = "C8 F7 G1 H11 H16 I3 K9 R9".split()
|
||||
|
||||
elif os.getenv('ICE384PINS'):
|
||||
num_ramb40 = 0
|
||||
|
||||
pins = """
|
||||
1 2 5 6 7 8
|
||||
12 13 14 15
|
||||
18 19 20 22 23
|
||||
26 27 29 30 31 32
|
||||
""".split()
|
||||
|
||||
gpins = "6 8 19 20 29 30".split()
|
||||
|
||||
else:
|
||||
num_ramb40 = 16
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
# - <project_name>.pcf ## physical constraint file
|
||||
#
|
||||
# Running iCEcube2:
|
||||
# - bash icecube.sh [-1k|-8k] <project_name> ## creates <project_name>.bin
|
||||
# - bash icecube.sh [-1k|-8k|-384] <project_name> ## creates <project_name>.bin
|
||||
#
|
||||
#
|
||||
#
|
||||
|
|
@ -41,6 +41,11 @@ if [ "$1" == "-8k" ]; then
|
|||
shift
|
||||
fi
|
||||
|
||||
if [ "$1" == "-384" ]; then
|
||||
ICEDEV=384-qn32
|
||||
shift
|
||||
fi
|
||||
|
||||
if [ "$1" == "-ul1k" ]; then
|
||||
ICEDEV=ul1k-cm36a
|
||||
shift
|
||||
|
|
@ -92,6 +97,10 @@ case "${ICEDEV:-hx1k-tq144}" in
|
|||
iCEPACKAGE="CB132"
|
||||
iCE40DEV="iCE40HX8K"
|
||||
;;
|
||||
lp384-qn32)
|
||||
iCEPACKAGE="QN32"
|
||||
iCE40DEV="iCE40LP384"
|
||||
;;
|
||||
lp1k-swg16tr)
|
||||
iCEPACKAGE="SWG16TR"
|
||||
iCE40DEV="iCE40LP1K"
|
||||
|
|
@ -177,6 +186,11 @@ case "$iCE40DEV" in
|
|||
libfile="ice40HX8K.lib"
|
||||
devfile="ICE40P08.dev"
|
||||
;;
|
||||
iCE40LP384)
|
||||
icetech="SBTiCE40"
|
||||
libfile="ice40LP384.lib"
|
||||
devfile="ICE40P03.dev"
|
||||
;;
|
||||
iCE40LP1K)
|
||||
icetech="SBTiCE40"
|
||||
libfile="ice40LP1K.lib"
|
||||
|
|
@ -380,5 +394,6 @@ if [ -n "$ICE_SBTIMER_LP" ]; then
|
|||
cp "$1.tmp"/outputs/netlist/top_timing_lp.rpt "$1.rlp"
|
||||
fi
|
||||
|
||||
export LD_LIBRARY_PATH=""
|
||||
$scriptdir/../icepack/iceunpack "$1.bin" "$1.asc"
|
||||
|
||||
|
|
|
|||
|
|
@ -9,15 +9,20 @@ os.mkdir("work_fanout")
|
|||
|
||||
for idx in range(num):
|
||||
with open("work_fanout/fanout_%02d.v" % idx, "w") as f:
|
||||
print("module top(input [1:0] a, output [63:0] y);", file=f)
|
||||
print(" assign y = {32{a}};", file=f)
|
||||
if os.getenv('ICE384PINS'):
|
||||
print("module top(input [1:0] a, output [15:0] y);", file=f)
|
||||
print(" assign y = {8{a}};", file=f)
|
||||
else:
|
||||
print("module top(input [1:0] a, output [63:0] y);", file=f)
|
||||
print(" assign y = {32{a}};", file=f)
|
||||
print("endmodule", file=f)
|
||||
with open("work_fanout/fanout_%02d.pcf" % idx, "w") as f:
|
||||
p = np.random.permutation(pins)
|
||||
for i in range(64):
|
||||
r = 16 if os.getenv('ICE384PINS') else 64
|
||||
for i in range(r):
|
||||
print("set_io y[%d] %s" % (i, p[i]), file=f)
|
||||
print("set_io a[0] %s" % p[64], file=f)
|
||||
print("set_io a[1] %s" % p[65], file=f)
|
||||
print("set_io a[0] %s" % p[r], file=f)
|
||||
print("set_io a[1] %s" % p[r+1], file=f)
|
||||
|
||||
with open("work_fanout/Makefile", "w") as f:
|
||||
print("all: %s" % " ".join(["fanout_%02d.bin" % i for i in range(num)]), file=f)
|
||||
|
|
|
|||
|
|
@ -37,8 +37,13 @@ def print_seq_op(dst, src1, src2, op, f):
|
|||
|
||||
for idx in range(num):
|
||||
with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f:
|
||||
print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f)
|
||||
print(" reg [15:0] p, q;", file=f)
|
||||
if os.getenv('ICE384PINS'):
|
||||
print("module top(input clk, rst, en, input [1:0] a, b, c, d, output [1:0] y, output z);", file=f)
|
||||
print(" reg [1:0] p, q;", file=f)
|
||||
else:
|
||||
print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f)
|
||||
print(" reg [15:0] p, q;", file=f)
|
||||
|
||||
print_seq_op("p", "a", "b", random_op(), f)
|
||||
print_seq_op("q", "c", "d", random_op(), f)
|
||||
print(" assign y = p %s q, z = clk ^ rst ^ en;" % random_op(), file=f)
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@ import os
|
|||
os.system("rm -rf work_gbio")
|
||||
os.mkdir("work_gbio")
|
||||
|
||||
w = 2 if os.getenv('ICE384PINS') else 8
|
||||
|
||||
for p in gpins:
|
||||
if p in pins: pins.remove(p)
|
||||
|
||||
|
|
@ -15,7 +17,7 @@ for idx in range(num):
|
|||
glbs = np.random.permutation(list(range(8)))
|
||||
print("""
|
||||
module top (
|
||||
inout [7:0] pin,
|
||||
inout [%s:0] pin,
|
||||
input latch_in,
|
||||
input clk_en,
|
||||
input clk_in,
|
||||
|
|
@ -23,9 +25,9 @@ for idx in range(num):
|
|||
input oen,
|
||||
input dout_0,
|
||||
input dout_1,
|
||||
output [7:0] din_0,
|
||||
output [7:0] din_1,
|
||||
output [7:0] globals,
|
||||
output [%s:0] din_0,
|
||||
output [%s:0] din_1,
|
||||
output [%s:0] globals,
|
||||
output reg q
|
||||
);
|
||||
SB_GB_IO #(
|
||||
|
|
@ -33,7 +35,7 @@ for idx in range(num):
|
|||
.PULLUP(1'b0),
|
||||
.NEG_TRIGGER(1'b0),
|
||||
.IO_STANDARD("SB_LVCMOS")
|
||||
) PINS [7:0] (
|
||||
) PINS [%s:0] (
|
||||
.PACKAGE_PIN(pin),
|
||||
.LATCH_INPUT_VALUE(%s),
|
||||
.CLOCK_ENABLE(%s),
|
||||
|
|
@ -54,6 +56,7 @@ for idx in range(num):
|
|||
q <= globals[%d];
|
||||
endmodule
|
||||
""" % (
|
||||
w-1, w-1, w-1, w-1, w-1,
|
||||
np.random.choice(["latch_in", "globals", "din_0+din_1", "din_0^din_1"]),
|
||||
np.random.choice(["clk_en", "globals", "din_0+din_1", "din_0^din_1"]),
|
||||
np.random.choice(["clk_in", "globals", "din_0+din_1", "din_0^din_1"]),
|
||||
|
|
@ -61,21 +64,24 @@ for idx in range(num):
|
|||
np.random.choice(["oen", "globals", "din_0+din_1", "din_0^din_1"]),
|
||||
np.random.choice(["dout_1", "globals", "globals^dout_0", "din_0+din_1", "~din_0"]),
|
||||
np.random.choice(["dout_0", "globals", "globals^dout_1", "din_0+din_1", "~din_1"]),
|
||||
np.random.choice(["din_0", "{din_0[3:0], din_0[7:4]}"]),
|
||||
np.random.choice(["din_1", "{din_1[1:0], din_1[7:2]}"]),
|
||||
np.random.choice(["globals", "{globals[0], globals[7:1]}"]),
|
||||
np.random.choice(["din_0", "{din_0[0], din_0[1]}"]) if os.getenv('ICE384PINS')
|
||||
else np.random.choice(["din_0", "{din_0[3:0], din_0[7:4]}"]) ,
|
||||
np.random.choice(["din_1", "{din_1[0], din_1[1]}"]) if os.getenv('ICE384PINS')
|
||||
else np.random.choice(["din_1", "{din_1[1:0], din_1[7:2]}"]),
|
||||
np.random.choice(["globals", "{globals[0], globals[1]}"]) if os.getenv('ICE384PINS')
|
||||
else np.random.choice(["globals", "{globals[0], globals[7:1]}"]),
|
||||
glbs[0], glbs[1], glbs[1], glbs[2], glbs[3]
|
||||
), file=f)
|
||||
with open("work_gbio/gbio_%02d.pcf" % idx, "w") as f:
|
||||
p = np.random.permutation(pins)
|
||||
g = np.random.permutation(gpins)
|
||||
for i in range(8):
|
||||
for i in range(w):
|
||||
print("set_io pin[%d] %s" % (i, g[i]), file=f)
|
||||
print("set_io din_0[%d] %s" % (i, p[8+i]), file=f)
|
||||
print("set_io din_1[%d] %s" % (i, p[2*8+i]), file=f)
|
||||
print("set_io globals[%d] %s" % (i, p[3*8+i]), file=f)
|
||||
print("set_io din_0[%d] %s" % (i, p[w+i]), file=f)
|
||||
print("set_io din_1[%d] %s" % (i, p[2*w+i]), file=f)
|
||||
print("set_io globals[%d] %s" % (i, p[3*w+i]), file=f)
|
||||
for i, n in enumerate("latch_in clk_en clk_in clk_out oen dout_0 dout_1".split()):
|
||||
print("set_io %s %s" % (n, p[4*8+i]), file=f)
|
||||
print("set_io %s %s" % (n, p[4*w+i]), file=f)
|
||||
print("set_io q %s" % (p[-1]), file=f)
|
||||
|
||||
with open("work_gbio/Makefile", "w") as f:
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@ import os
|
|||
os.system("rm -rf work_gbio2")
|
||||
os.mkdir("work_gbio2")
|
||||
|
||||
w = 2 if os.getenv('ICE384PINS') else 8
|
||||
|
||||
for p in gpins:
|
||||
if p in pins: pins.remove(p)
|
||||
|
||||
|
|
@ -15,7 +17,7 @@ for idx in range(num):
|
|||
glbs = np.random.permutation(list(range(8)))
|
||||
print("""
|
||||
module top (
|
||||
inout [7:0] pin,
|
||||
inout [%s:0] pin,
|
||||
input latch_in,
|
||||
input clk_en,
|
||||
input clk_in,
|
||||
|
|
@ -23,13 +25,15 @@ for idx in range(num):
|
|||
input oen,
|
||||
input dout_0,
|
||||
input dout_1,
|
||||
output [7:0] din_0,
|
||||
output [7:0] din_1,
|
||||
output [7:0] globals,
|
||||
output [%s:0] din_0,
|
||||
output [%s:0] din_1,
|
||||
output [%s:0] globals,
|
||||
output reg q
|
||||
);
|
||||
""", file=f);
|
||||
for k in range(8):
|
||||
""" % (
|
||||
w-1, w-1, w-1, w-1
|
||||
), file=f);
|
||||
for k in range(w):
|
||||
print("""
|
||||
SB_GB_IO #(
|
||||
.PIN_TYPE(6'b %s),
|
||||
|
|
@ -68,13 +72,13 @@ for idx in range(num):
|
|||
with open("work_gbio2/gbio2_%02d.pcf" % idx, "w") as f:
|
||||
p = np.random.permutation(pins)
|
||||
g = np.random.permutation(gpins)
|
||||
for i in range(8):
|
||||
for i in range(w):
|
||||
print("set_io pin[%d] %s" % (i, g[i]), file=f)
|
||||
print("set_io din_0[%d] %s" % (i, p[8+i]), file=f)
|
||||
print("set_io din_1[%d] %s" % (i, p[2*8+i]), file=f)
|
||||
print("set_io globals[%d] %s" % (i, p[3*8+i]), file=f)
|
||||
print("set_io din_0[%d] %s" % (i, p[w+i]), file=f)
|
||||
print("set_io din_1[%d] %s" % (i, p[2*w+i]), file=f)
|
||||
print("set_io globals[%d] %s" % (i, p[3*w+i]), file=f)
|
||||
for i, n in enumerate("latch_in clk_en clk_in clk_out oen dout_0 dout_1".split()):
|
||||
print("set_io %s %s" % (n, p[4*8+i]), file=f)
|
||||
print("set_io %s %s" % (n, p[4*w+i]), file=f)
|
||||
print("set_io q %s" % (p[-1]), file=f)
|
||||
|
||||
with open("work_gbio2/Makefile", "w") as f:
|
||||
|
|
|
|||
|
|
@ -7,28 +7,31 @@ import os
|
|||
os.system("rm -rf work_io")
|
||||
os.mkdir("work_io")
|
||||
|
||||
if os.getenv('ICE384PINS'): w = 2
|
||||
else: w = 4
|
||||
|
||||
for idx in range(num):
|
||||
with open("work_io/io_%02d.v" % idx, "w") as f:
|
||||
glbs = np.random.permutation(list(range(8)))
|
||||
print("""
|
||||
module top (
|
||||
inout [3:0] pin,
|
||||
input [3:0] latch_in,
|
||||
input [3:0] clk_en,
|
||||
input [3:0] clk_in,
|
||||
input [3:0] clk_out,
|
||||
input [3:0] oen,
|
||||
input [3:0] dout_0,
|
||||
input [3:0] dout_1,
|
||||
output [3:0] din_0,
|
||||
output [3:0] din_1
|
||||
inout [%s:0] pin,
|
||||
input [%s:0] latch_in,
|
||||
input [%s:0] clk_en,
|
||||
input [%s:0] clk_in,
|
||||
input [%s:0] clk_out,
|
||||
input [%s:0] oen,
|
||||
input [%s:0] dout_0,
|
||||
input [%s:0] dout_1,
|
||||
output [%s:0] din_0,
|
||||
output [%s:0] din_1
|
||||
);
|
||||
SB_IO #(
|
||||
.PIN_TYPE(6'b %s_%s),
|
||||
.PULLUP(1'b %s),
|
||||
.NEG_TRIGGER(1'b %s),
|
||||
.IO_STANDARD("SB_LVCMOS")
|
||||
) PINS [3:0] (
|
||||
) PINS [%s:0] (
|
||||
.PACKAGE_PIN(pin),
|
||||
.LATCH_INPUT_VALUE(latch_in),
|
||||
.CLOCK_ENABLE(clk_en),
|
||||
|
|
@ -42,13 +45,14 @@ for idx in range(num):
|
|||
);
|
||||
endmodule
|
||||
""" % (
|
||||
w-1, w-1, w-1, w-1, w-1, w-1, w-1, w-1, w-1, w-1,
|
||||
np.random.choice(["0000", "0110", "1010", "1110", "0101", "1001", "1101", "0100", "1000", "1100", "0111", "1111"]),
|
||||
np.random.choice(["00", "01", "10", "11"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"])
|
||||
np.random.choice(["00", "01", "10", "11"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"]), w-1
|
||||
), file=f)
|
||||
with open("work_io/io_%02d.pcf" % idx, "w") as f:
|
||||
p = list(np.random.permutation(pins))
|
||||
for k in ["pin", "latch_in", "clk_en", "clk_in", "clk_out", "oen", "dout_0", "dout_1", "din_0", "din_1"]:
|
||||
for i in range(4):
|
||||
for i in range(w):
|
||||
print("set_io %s[%d] %s" % (k, i, p.pop()), file=f)
|
||||
|
||||
with open("work_io/Makefile", "w") as f:
|
||||
|
|
|
|||
|
|
@ -12,17 +12,21 @@ def random_op():
|
|||
|
||||
for idx in range(num):
|
||||
with open("work_logic/logic_%02d.v" % idx, "w") as f:
|
||||
print("module top(input [15:0] a, b, c, d, output [15:0] y);", file=f)
|
||||
if os.getenv('ICE384PINS'):
|
||||
print("module top(input [3:0] a, b, c, d, output [3:0] y);", file=f)
|
||||
else:
|
||||
print("module top(input [15:0] a, b, c, d, output [15:0] y);", file=f)
|
||||
print(" assign y = (a %s b) %s (c %s d);" % (random_op(), random_op(), random_op()), file=f)
|
||||
print("endmodule", file=f)
|
||||
with open("work_logic/logic_%02d.pcf" % idx, "w") as f:
|
||||
p = np.random.permutation(pins)
|
||||
for i in range(16):
|
||||
r = 4 if os.getenv('ICE384PINS') else 16
|
||||
for i in range(r):
|
||||
print("set_io a[%d] %s" % (i, p[i]), file=f)
|
||||
print("set_io b[%d] %s" % (i, p[i+16]), file=f)
|
||||
print("set_io c[%d] %s" % (i, p[i+32]), file=f)
|
||||
print("set_io d[%d] %s" % (i, p[i+48]), file=f)
|
||||
print("set_io y[%d] %s" % (i, p[i+64]), file=f)
|
||||
print("set_io b[%d] %s" % (i, p[i+r]), file=f)
|
||||
print("set_io c[%d] %s" % (i, p[i+r*2]), file=f)
|
||||
print("set_io d[%d] %s" % (i, p[i+r*3]), file=f)
|
||||
print("set_io y[%d] %s" % (i, p[i+r*4]), file=f)
|
||||
|
||||
with open("work_logic/Makefile", "w") as f:
|
||||
print("all: %s" % " ".join(["logic_%02d.bin" % i for i in range(num)]), file=f)
|
||||
|
|
|
|||
|
|
@ -9,15 +9,20 @@ os.mkdir("work_mesh")
|
|||
|
||||
for idx in range(num):
|
||||
with open("work_mesh/mesh_%02d.v" % idx, "w") as f:
|
||||
print("module top(input [39:0] a, output [39:0] y);", file=f)
|
||||
if os.getenv('ICE384PINS'):
|
||||
print("module top(input [9:0] a, output [9:0] y);", file=f)
|
||||
else:
|
||||
print("module top(input [39:0] a, output [39:0] y);", file=f)
|
||||
print(" assign y = a;", file=f)
|
||||
print("endmodule", file=f)
|
||||
with open("work_mesh/mesh_%02d.pcf" % idx, "w") as f:
|
||||
p = np.random.permutation(pins)
|
||||
for i in range(40):
|
||||
if os.getenv('ICE384PINS'): r = 10
|
||||
else: r = 40
|
||||
for i in range(r):
|
||||
print("set_io a[%d] %s" % (i, p[i]), file=f)
|
||||
for i in range(40):
|
||||
print("set_io y[%d] %s" % (i, p[40+i]), file=f)
|
||||
for i in range(r):
|
||||
print("set_io y[%d] %s" % (i, p[r+i]), file=f)
|
||||
|
||||
with open("work_mesh/Makefile", "w") as f:
|
||||
print("all: %s" % " ".join(["mesh_%02d.bin" % i for i in range(num)]), file=f)
|
||||
|
|
|
|||
|
|
@ -7,11 +7,13 @@ import os
|
|||
os.system("rm -rf work_prim")
|
||||
os.mkdir("work_prim")
|
||||
|
||||
w = 5 if os.getenv('ICE384PINS') else 24
|
||||
|
||||
for idx in range(num):
|
||||
with open("work_prim/prim_%02d.v" % idx, "w") as f:
|
||||
clkedge = np.random.choice(["pos", "neg"])
|
||||
print("module top(input clk, input [23:0] a, b, output reg x, output reg [23:0] y);", file=f)
|
||||
print(" reg [23:0] aa, bb;", file=f)
|
||||
print("module top(input clk, input [%s:0] a, b, output reg x, output reg [%s:0] y);""" % ( w-1, w-1 ), file=f)
|
||||
print(" reg [%s:0] aa, bb;""" % ( w-1 ), file=f)
|
||||
print(" always @(%sedge clk) aa <= a;" % clkedge, file=f)
|
||||
print(" always @(%sedge clk) bb <= b;" % clkedge, file=f)
|
||||
if np.random.choice([True, False]):
|
||||
|
|
@ -26,20 +28,20 @@ for idx in range(num):
|
|||
with open("work_prim/prim_%02d.pcf" % idx, "w") as f:
|
||||
p = np.random.permutation(pins)
|
||||
if np.random.choice([True, False]):
|
||||
for i in range(24):
|
||||
for i in range(w):
|
||||
print("set_io a[%d] %s" % (i, p[i]), file=f)
|
||||
if np.random.choice([True, False]):
|
||||
for i in range(24):
|
||||
print("set_io b[%d] %s" % (i, p[24+i]), file=f)
|
||||
for i in range(w):
|
||||
print("set_io b[%d] %s" % (i, p[w+i]), file=f)
|
||||
if np.random.choice([True, False]):
|
||||
for i in range(24):
|
||||
print("set_io y[%d] %s" % (i, p[2*24+i]), file=f)
|
||||
for i in range(w):
|
||||
print("set_io y[%d] %s" % (i, p[2*w+i]), file=f)
|
||||
if np.random.choice([True, False]):
|
||||
print("set_io x %s" % p[3*24], file=f)
|
||||
print("set_io x %s" % p[3*w], file=f)
|
||||
if np.random.choice([True, False]):
|
||||
print("set_io y %s" % p[3*24+1], file=f)
|
||||
print("set_io y %s" % p[3*w+1], file=f)
|
||||
if np.random.choice([True, False]):
|
||||
print("set_io clk %s" % p[3*24+2], file=f)
|
||||
print("set_io clk %s" % p[3*w+2], file=f)
|
||||
|
||||
with open("work_prim/Makefile", "w") as f:
|
||||
print("all: %s" % " ".join(["prim_%02d.bin" % i for i in range(num)]), file=f)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
#!/bin/bash
|
||||
|
||||
mkdir -p pinloc-384-qn32
|
||||
cd pinloc-384-qn32
|
||||
|
||||
pins="
|
||||
1 2 5 6 7 8
|
||||
12 13 14 15
|
||||
18 19 20 22 23
|
||||
26 27 29 30 31 32
|
||||
"
|
||||
|
||||
if [ $(echo $pins | wc -w) -ne 21 ]; then
|
||||
echo "Incorrect number of pins:" $(echo $pins | wc -w)
|
||||
exit 1
|
||||
fi
|
||||
|
||||
{
|
||||
echo -n "all:"
|
||||
for pin in $pins; do
|
||||
id="pinloc-384-qn32_${pin}"
|
||||
echo -n " ${id}.exp"
|
||||
done
|
||||
echo
|
||||
|
||||
for pin in $pins; do
|
||||
id="pinloc-384-qn32_${pin}"
|
||||
echo "module top(output y); assign y = 0; endmodule" > ${id}.v
|
||||
echo "set_io y ${pin}" >> ${id}.pcf
|
||||
echo; echo "${id}.exp:"
|
||||
echo " ICEDEV=384-qn32 bash ../../icecube.sh ${id} > ${id}.log 2>&1"
|
||||
echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new"
|
||||
echo " ! grep '^Warning: pin' ${id}.log"
|
||||
echo " rm -rf ${id}.tmp"
|
||||
echo " mv ${id}.exp.new ${id}.exp"
|
||||
done
|
||||
} > pinloc-384-qn32.mk
|
||||
|
||||
set -ex
|
||||
make -f pinloc-384-qn32.mk -j4
|
||||
python3 ../pinlocdb.py pinloc-384-qn32_*.exp > ../pinloc-384-qn32.txt
|
||||
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
CELL CascadeBuf
|
||||
IOPATH I O 137.402:178.5:217.075 170.116:221:268.76
|
||||
|
||||
CELL CascadeMux
|
||||
IOPATH I O 0:0:0 0:0:0
|
||||
|
||||
CELL CEMux
|
||||
IOPATH I O 562.692:731:888.975 516.892:671.5:816.617
|
||||
|
||||
CELL ClkMux
|
||||
IOPATH I O 287.889:374:454.825 215.917:280.5:341.118
|
||||
|
||||
CELL gio2CtrlBuf
|
||||
IOPATH I O 0:0:0 0:0:0
|
||||
|
||||
CELL Glb2LocalMux
|
||||
IOPATH I O 418.748:544:661.563 333.689:433.5:527.183
|
||||
|
||||
CELL GlobalMux
|
||||
IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706
|
||||
|
||||
CELL ICE_GB
|
||||
IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954
|
||||
|
||||
CELL InMux
|
||||
IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
|
||||
|
||||
CELL INV
|
||||
IOPATH I O 0:0:0 0:0:0
|
||||
|
||||
CELL IO_PAD
|
||||
IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
|
||||
IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990
|
||||
IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942
|
||||
IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
|
||||
IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540
|
||||
|
||||
CELL IoInMux
|
||||
IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
|
||||
|
||||
CELL IoSpan4Mux
|
||||
IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
|
||||
|
||||
CELL LocalMux
|
||||
IOPATH I O 307.518:399.5:485.835 287.889:374:454.825
|
||||
|
||||
CELL LogicCell40
|
||||
HOLD negedge:ce posedge:clk 0:0:0
|
||||
HOLD negedge:in0 posedge:clk 0:0:0
|
||||
HOLD negedge:in1 posedge:clk 0:0:0
|
||||
HOLD negedge:in2 posedge:clk 0:0:0
|
||||
HOLD negedge:in3 posedge:clk 0:0:0
|
||||
HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984
|
||||
HOLD posedge:ce posedge:clk 0:0:0
|
||||
HOLD posedge:in0 posedge:clk 0:0:0
|
||||
HOLD posedge:in1 posedge:clk 0:0:0
|
||||
HOLD posedge:in2 posedge:clk 0:0:0
|
||||
HOLD posedge:in3 posedge:clk 0:0:0
|
||||
HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005
|
||||
RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372
|
||||
RECOVERY posedge:sr posedge:clk 0:0:0
|
||||
REMOVAL negedge:sr posedge:clk 0:0:0
|
||||
REMOVAL posedge:sr posedge:clk 0:0:0
|
||||
SETUP negedge:ce posedge:clk 0:0:0
|
||||
SETUP negedge:in0 posedge:clk 372.947:484.5:589.205
|
||||
SETUP negedge:in1 posedge:clk 353.318:459:558.194
|
||||
SETUP negedge:in2 posedge:clk 300.975:391:475.498
|
||||
SETUP negedge:in3 posedge:clk 202.831:263.5:320.445
|
||||
SETUP negedge:sr posedge:clk 130.859:170:206.738
|
||||
SETUP posedge:ce posedge:clk 0:0:0
|
||||
SETUP posedge:in0 posedge:clk 438.376:569.5:692.574
|
||||
SETUP posedge:in1 posedge:clk 372.947:484.5:589.205
|
||||
SETUP posedge:in2 posedge:clk 346.775:450.5:547.857
|
||||
SETUP posedge:in3 posedge:clk 255.174:331.5:403.14
|
||||
SETUP posedge:sr posedge:clk 189.745:246.5:299.771
|
||||
IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054
|
||||
IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531
|
||||
IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531
|
||||
IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792
|
||||
IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194
|
||||
IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194
|
||||
IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402
|
||||
IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846
|
||||
IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509
|
||||
IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814
|
||||
IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14
|
||||
IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943
|
||||
IOPATH sr lcout 0:0:0 558.989:726.189:883.125
|
||||
IOPATH sr lcout 558.963:726.155:883.083 0:0:0
|
||||
|
||||
CELL Odrv4
|
||||
IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
|
||||
|
||||
CELL Odrv12
|
||||
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
|
||||
|
||||
CELL PRE_IO
|
||||
HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
|
||||
HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
|
||||
HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0
|
||||
HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0
|
||||
HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
|
||||
HOLD negedge:PADIN negedge:INPUTCLK -785.152:-1020:-1240.43
|
||||
HOLD negedge:PADIN posedge:INPUTCLK -785.152:-1020:-1240.43
|
||||
HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
|
||||
HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
|
||||
HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0
|
||||
HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0
|
||||
HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
|
||||
HOLD posedge:PADIN negedge:INPUTCLK -785.152:-1020:-1240.43
|
||||
HOLD posedge:PADIN posedge:INPUTCLK -785.152:-1020:-1240.43
|
||||
SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369
|
||||
SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369
|
||||
SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369
|
||||
SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369
|
||||
SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369
|
||||
SETUP negedge:PADIN negedge:INPUTCLK 1962.88:2550:3101.08
|
||||
SETUP negedge:PADIN posedge:INPUTCLK 1962.88:2550:3101.08
|
||||
SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706
|
||||
SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
|
||||
SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706
|
||||
SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706
|
||||
SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
|
||||
SETUP posedge:PADIN negedge:INPUTCLK 1969.42:2558.5:3111.41
|
||||
SETUP posedge:PADIN posedge:INPUTCLK 1969.42:2558.5:3111.41
|
||||
IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48
|
||||
IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857
|
||||
IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738
|
||||
IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
|
||||
IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108
|
||||
IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237
|
||||
IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738
|
||||
IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738
|
||||
IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
|
||||
|
||||
CELL PRE_IO_GBUF
|
||||
IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1583.39:2057:2501.54 1439.44:1870:2274.12
|
||||
|
||||
CELL Sp12to4
|
||||
IOPATH I O 399.119:518.5:630.552 418.748:544:661.563
|
||||
|
||||
CELL Span4Mux_h0
|
||||
IOPATH I O 137.402:178.5:217.075 130.859:170:206.738
|
||||
|
||||
CELL Span4Mux_h1
|
||||
IOPATH I O 163.573:212.5:258.423 157.03:204:248.086
|
||||
|
||||
CELL Span4Mux_h2
|
||||
IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771
|
||||
|
||||
CELL Span4Mux_h3
|
||||
IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118
|
||||
|
||||
CELL Span4Mux_h4
|
||||
IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161
|
||||
|
||||
CELL Span4Mux_v0
|
||||
IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097
|
||||
|
||||
CELL Span4Mux_v1
|
||||
IOPATH I O 189.745:246.5:299.771 183.202:238:289.434
|
||||
|
||||
CELL Span4Mux_v2
|
||||
IOPATH I O 235.546:306:372.129 235.546:306:372.129
|
||||
|
||||
CELL Span4Mux_v3
|
||||
IOPATH I O 294.432:382.5:465.161 314.061:408:496.172
|
||||
|
||||
CELL Span4Mux_v4
|
||||
IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
|
||||
|
||||
CELL Span12Mux_h0
|
||||
IOPATH I O 130.859:170:206.738 137.402:178.5:217.075
|
||||
|
||||
CELL Span12Mux_h1
|
||||
IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402
|
||||
|
||||
CELL Span12Mux_h2
|
||||
IOPATH I O 150.487:195.5:237.749 157.03:204:248.086
|
||||
|
||||
CELL Span12Mux_h3
|
||||
IOPATH I O 157.03:204:248.086 170.116:221:268.76
|
||||
|
||||
CELL Span12Mux_h4
|
||||
IOPATH I O 183.202:238:289.434 202.831:263.5:320.445
|
||||
|
||||
CELL Span12Mux_h5
|
||||
IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466
|
||||
|
||||
CELL Span12Mux_h6
|
||||
IOPATH I O 235.546:306:372.129 261.717:340:413.477
|
||||
|
||||
CELL Span12Mux_h7
|
||||
IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
|
||||
|
||||
CELL Span12Mux_h8
|
||||
IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531
|
||||
|
||||
CELL Span12Mux_h9
|
||||
IOPATH I O 366.404:476:578.868 405.662:527:640.889
|
||||
|
||||
CELL Span12Mux_h10
|
||||
IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574
|
||||
|
||||
CELL Span12Mux_h11
|
||||
IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269
|
||||
|
||||
CELL Span12Mux_h12
|
||||
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
|
||||
|
||||
CELL Span12Mux_v0
|
||||
IOPATH I O 91.601:119:144.717 98.144:127.5:155.054
|
||||
|
||||
CELL Span12Mux_v1
|
||||
IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054
|
||||
|
||||
CELL Span12Mux_v2
|
||||
IOPATH I O 130.859:170:206.738 143.944:187:227.412
|
||||
|
||||
CELL Span12Mux_v3
|
||||
IOPATH I O 137.402:178.5:217.075 157.03:204:248.086
|
||||
|
||||
CELL Span12Mux_v4
|
||||
IOPATH I O 170.116:221:268.76 196.288:255:310.108
|
||||
|
||||
CELL Span12Mux_v5
|
||||
IOPATH I O 222.46:289:351.455 248.631:323:392.803
|
||||
|
||||
CELL Span12Mux_v6
|
||||
IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814
|
||||
|
||||
CELL Span12Mux_v7
|
||||
IOPATH I O 261.717:340:413.477 294.432:382.5:465.161
|
||||
|
||||
CELL Span12Mux_v8
|
||||
IOPATH I O 333.689:433.5:527.183 366.404:476:578.868
|
||||
|
||||
CELL Span12Mux_v9
|
||||
IOPATH I O 353.318:459:558.194 392.576:510:620.215
|
||||
|
||||
CELL Span12Mux_v10
|
||||
IOPATH I O 366.404:476:578.868 405.662:527:640.889
|
||||
|
||||
CELL Span12Mux_v11
|
||||
IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9
|
||||
|
||||
CELL Span12Mux_v12
|
||||
IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
|
||||
|
||||
CELL SRMux
|
||||
IOPATH I O 431.833:561:682.237 333.689:433.5:527.183
|
||||
|
||||
|
|
@ -688,6 +688,7 @@ Span4Mux_s2_h.O Span4Mux_h.I
|
|||
Span4Mux_s2_h.O Span4Mux_s0_v.I
|
||||
Span4Mux_s2_h.O Span4Mux_s1_v.I
|
||||
Span4Mux_s2_h.O Span4Mux_s2_v.I
|
||||
Span4Mux_s2_h.O Span4Mux_s3_h.I
|
||||
Span4Mux_s2_h.O Span4Mux_s3_v.I
|
||||
Span4Mux_s2_h.O Span4Mux_v.I
|
||||
Span4Mux_s2_v.O IoSpan4Mux.I
|
||||
|
|
@ -703,6 +704,7 @@ Span4Mux_s3_h.O LocalMux.I
|
|||
Span4Mux_s3_h.O Span4Mux_h.I
|
||||
Span4Mux_s3_h.O Span4Mux_s0_v.I
|
||||
Span4Mux_s3_h.O Span4Mux_s1_v.I
|
||||
Span4Mux_s3_h.O Span4Mux_s2_h.I
|
||||
Span4Mux_s3_h.O Span4Mux_s2_v.I
|
||||
Span4Mux_s3_h.O Span4Mux_s3_v.I
|
||||
Span4Mux_s3_h.O Span4Mux_v.I
|
||||
|
|
|
|||
Loading…
Reference in New Issue