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Merge pull request #151 from mithro/hlc-lut-init 

icebox_hlc2asc: Allow truth tables to be specified as init string.
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Clifford Wolf 2018-06-13 13:44:04 +02:00 committed by GitHub
parent 73e2ddb7c7 ee84ee4d1b
commit 25cda32bb8
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1 changed files with 13 additions and 2 deletions
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15
icebox/icebox_hlc2asc.py
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@ -832,8 +832,19 @@ class LogicCell:
if fields[0] == 'lut' and len(fields) == 2 and self.lut_bits is None: if fields[0] == 'lut' and len(fields) == 2 and self.lut_bits is None:
self.lut_bits = fields[1] self.lut_bits = fields[1]
elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=': elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=':
self.lut_bits = logic_expression_to_lut( m = re.match("([0-9]+)'b([01]+)", fields[2])
' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3')) if m:
lut_bits = m.group(2)
if len(lut_bits) != int(m.group(1)):
raise ParseError
m = len(lut_bits)
if m < 16:
lut_bits = (16-m) * "0" + lut_bits
# Verilog 16'bXXXX is MSB first but the bitstream wants LSB.
self.lut_bits = lut_bits[::-1]
else:
self.lut_bits = logic_expression_to_lut(
' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3'))
elif fields == ['enable_carry']: elif fields == ['enable_carry']:
self.seq_bits[0] = '1' self.seq_bits[0] = '1'
elif fields == ['enable_dff']: elif fields == ['enable_dff']: