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Fixed SBTICETechnologyLibrary links

This commit is contained in:
Clifford Wolf 2015-08-15 10:07:30 +02:00
parent 4ab236aae7
commit 235ff955e3
2 changed files with 2 additions and 2 deletions
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2
docs/index.html
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@ -144,7 +144,7 @@ create an IceBox ASCII file for the placed and routed design.
<p>
Recommended reading:
<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf">Lattice iCE40 LP/HX Family Datasheet</a>,
<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201412.pdf">Lattice iCE Technology Library</a>
<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201504.pdf">Lattice iCE Technology Library</a>
(Especially the three pages on "Architecture Overview", "PLB Blocks", "Routing", and "Clock/Control Distribution Network" in
the Lattice iCE40 LP/HX Family Datasheet. Read that first, then come back here.)
</p>

2
docs/io_tile.html
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@ -46,7 +46,7 @@ connecting IO tiles to each other are not pairwise crossed out.
<p>
Each IO tile contains two IO blocks. Each IO block essentially implements the <tt>SB_IO</tt>
primitive from the <a href="http://www.latticesemi.com/~/media/Documents/TechnicalBriefs/iCETechnologyLibrary.PDF">Lattice iCE Technology Library</a>.
primitive from the Lattice iCE Technology Library.
Some inputs are shared between the two IO blocks. The following table lists how the
wires in the logic tile map to the <tt>SB_IO</tt> primitive ports:
</p>