mirror of https://github.com/YosysHQ/icestorm.git
icetime progress
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062d07e2db
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22e1f33d90
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@ -88,6 +88,7 @@ std::map<std::string, std::string> netlist_cell_types;
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std::set<std::string> extra_wires;
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std::vector<std::string> extra_vlog;
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std::set<int> declared_nets;
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int dangling_cnt = 0;
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std::map<std::string, std::vector<std::pair<int, int>>> logic_tile_bits,
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io_tile_bits, ramb_tile_bits, ramt_tile_bits;
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@ -635,6 +636,37 @@ std::string make_lc40(int x, int y, int z)
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return cell;
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}
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std::string make_ram(int x, int y)
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{
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auto cell = stringf("ram_%d_%d", x, y);
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if (netlist_cell_types.count(cell))
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return cell;
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netlist_cell_types[cell] = "SB_RAM40_4K";
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for (int i = 0; i < 16; i++) {
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netlist_cells[cell][stringf("MASK[%d]", i)] = "";
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netlist_cells[cell][stringf("RDATA[%d]", i)] = "";
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netlist_cells[cell][stringf("WDATA[%d]", i)] = "";
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}
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for (int i = 0; i < 11; i++) {
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netlist_cells[cell][stringf("RADDR[%d]", i)] = "";
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netlist_cells[cell][stringf("WADDR[%d]", i)] = "";
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}
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netlist_cells[cell]["RE"] = "";
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netlist_cells[cell]["RCLK"] = "";
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netlist_cells[cell]["RCLKE"] = "";
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netlist_cells[cell]["WE"] = "";
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netlist_cells[cell]["WCLK"] = "";
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netlist_cells[cell]["WCLKE"] = "";
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return cell;
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}
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bool dff_uses_clock(int x, int y, int z)
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{
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auto bitpos = logic_tile_bits[stringf("LC_%d", z)][9];
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@ -705,6 +737,14 @@ void make_inmux(int x, int y, int dst, std::string muxtype = "")
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}
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}
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std::string cascademuxed(std::string n)
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{
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std::string nc = n + "_cascademuxed";
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extra_wires.insert(nc);
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extra_vlog.push_back(stringf(" CascadeMux %s (.I(%s), .O(%s));\n", tname().c_str(), n.c_str(), nc.c_str()));
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return nc;
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}
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void make_seg_cell(int net, const net_segment_t &seg)
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{
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int a = -1, b = -1;
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@ -728,10 +768,7 @@ void make_seg_cell(int net, const net_segment_t &seg)
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auto cell = make_lc40(seg.x, seg.y, a);
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if (b == 2) {
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// Lattice tools always put a CascadeMux on in2
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extra_wires.insert(net_name(net) + "_cascademuxed");
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extra_vlog.push_back(stringf(" CascadeMux %s (.I(%s), .O(%s));\n",
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tname().c_str(), net_name(net).c_str(), (net_name(net) + "_cascademuxed").c_str()));
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netlist_cells[cell][stringf("in%d", b)] = net_name(net) + "_cascademuxed";
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netlist_cells[cell][stringf("in%d", b)] = cascademuxed(net_name(net));
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} else {
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netlist_cells[cell][stringf("in%d", b)] = net_name(net);
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}
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@ -764,6 +801,40 @@ void make_seg_cell(int net, const net_segment_t &seg)
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return;
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}
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if (seg.name.substr(0, 4) == "ram/")
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{
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auto cell = make_ram(seg.x, 2*((seg.y-1) >> 1) + 1);
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if (sscanf(seg.name.c_str(), "ram/MASK_%d", &a) == 1) {
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netlist_cells[cell][stringf("MASK[%d]", a)] = net_name(net);
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make_inmux(seg.x, seg.y, net);
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} else
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if (sscanf(seg.name.c_str(), "ram/RADDR_%d", &a) == 1) {
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netlist_cells[cell][stringf("RADDR[%d]", a)] = cascademuxed(net_name(net));
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make_inmux(seg.x, seg.y, net);
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} else
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if (sscanf(seg.name.c_str(), "ram/RDATA_%d", &a) == 1) {
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netlist_cells[cell][stringf("RDATA[%d]", a)] = net_name(net);
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make_odrv(seg.x, seg.y, net);
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} else
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if (sscanf(seg.name.c_str(), "ram/WADDR_%d", &a) == 1) {
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netlist_cells[cell][stringf("WADDR[%d]", a)] = cascademuxed(net_name(net));
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make_inmux(seg.x, seg.y, net);
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} else
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if (sscanf(seg.name.c_str(), "ram/WDATA_%d", &a) == 1) {
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netlist_cells[cell][stringf("WDATA[%d]", a)] = net_name(net);
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make_inmux(seg.x, seg.y, net);
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} else {
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netlist_cells[cell][seg.name.substr(4)] = net_name(net);
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if (seg.name == "ram/RCLK" || seg.name == "ram/WCLK")
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make_inmux(seg.x, seg.y, net, "ClkMux");
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else
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make_inmux(seg.x, seg.y, net, "SRMux");
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}
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return;
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}
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if (seg.name == "lutff_global/clk")
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{
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for (int i = 0; i < 8; i++)
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@ -785,15 +856,23 @@ void make_seg_cell(int net, const net_segment_t &seg)
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{
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for (int i = 0; i < 2; i++)
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{
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std::tuple<int, int, std::string> din0_key(seg.x, seg.y, stringf("io_%d/D_IN_%d", i, 0));
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std::tuple<int, int, std::string> din1_key(seg.x, seg.y, stringf("io_%d/D_IN_%d", i, 1));
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if (seg.name == "io_global/inclk")
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{
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std::tuple<int, int, std::string> din0_key(seg.x, seg.y, stringf("io_%d/D_IN_%d", i, 0));
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std::tuple<int, int, std::string> din1_key(seg.x, seg.y, stringf("io_%d/D_IN_%d", i, 1));
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std::tuple<int, int, std::string> dout0_key(seg.x, seg.y, stringf("io_%d/D_OUT_%d", i, 0));
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std::tuple<int, int, std::string> dout1_key(seg.x, seg.y, stringf("io_%d/D_OUT_%d", i, 1));
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if (x_y_name_net.count(din0_key) == 0 && x_y_name_net.count(din1_key) == 0)
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continue;
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}
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if (x_y_name_net.count(din0_key) == 0 && x_y_name_net.count(din1_key) == 0 &&
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x_y_name_net.count(dout0_key) == 0 && x_y_name_net.count(dout1_key) == 0)
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continue;
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if (seg.name == "io_global/outclk")
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{
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std::tuple<int, int, std::string> dout0_key(seg.x, seg.y, stringf("io_%d/D_OUT_%d", i, 0));
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std::tuple<int, int, std::string> dout1_key(seg.x, seg.y, stringf("io_%d/D_OUT_%d", i, 1));
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if (x_y_name_net.count(dout0_key) == 0 && x_y_name_net.count(dout1_key) == 0)
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continue;
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}
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auto cell = make_seg_pre_io(seg.x, seg.y, i);
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@ -1290,7 +1369,8 @@ int main(int argc, char **argv)
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for (auto &str : extra_vlog)
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fprintf(fout, "%s", str.c_str());
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for (auto it : netlist_cell_types) {
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for (auto it : netlist_cell_types)
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{
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const char *sep = "";
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fprintf(fout, " %s ", it.second.c_str());
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if (netlist_cell_params.count(it.first)) {
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@ -1302,11 +1382,42 @@ int main(int argc, char **argv)
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fprintf(fout, "\n ) ");
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sep = "";
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}
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fprintf(fout, "%s (", it.first.c_str());
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for (auto port : netlist_cells[it.first]) {
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std::map<std::string, std::vector<std::string>> multibit_ports;
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for (auto port : netlist_cells[it.first])
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{
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size_t open_bracket_pos = port.first.find('[');
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if (open_bracket_pos != std::string::npos) {
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std::string base_name = port.first.substr(0, open_bracket_pos);
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int bit_index = atoi(port.first.substr(open_bracket_pos+1).c_str());
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if (multibit_ports[base_name].size() <= bit_index)
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multibit_ports[base_name].resize(bit_index+1);
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multibit_ports[base_name][bit_index] = port.second;
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continue;
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}
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fprintf(fout, "%s\n .%s(%s)", sep, port.first.c_str(), port.second.c_str());
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sep = ",";
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}
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for (auto it : multibit_ports)
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{
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fprintf(fout, "%s\n .%s({", sep, it.first.c_str());
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sep = ",";
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const char *sepsep = "";
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for (int i = int(it.second.size())-1; i >= 0; i--) {
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std::string wire_name = it.second[i];
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if (wire_name == "")
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wire_name = stringf("dangling_wire_%d", dangling_cnt++);
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fprintf(fout, "%s%s", sepsep, wire_name.c_str());
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sepsep = ", ";
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}
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fprintf(fout, "})");
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}
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fprintf(fout, "\n );\n");
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}
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@ -96,7 +96,7 @@ os.rename("%s.v" % sys.argv[1], "%s_in.v" % sys.argv[1])
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with open("%s_ref.v" % sys.argv[1], "w") as f:
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for line in open("%s.vsb" % sys.argv[1], "r"):
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if re.match(r" *defparam .*\.(IO_STANDARD|PULLUP)=", line):
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if re.match(r" *defparam .*\.(IO_STANDARD|PULLUP|INIT_.|WRITE_MODE|READ_MODE)=", line):
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continue
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line = line.replace(" Span4Mux_s0_h ", " Span4Mux_h4 " if max_span_hack else " Span4Mux_h0 ")
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