mirror of https://github.com/YosysHQ/icestorm.git
Merge pull request #110 from daveshah1/up5k_ip
UltraPlus Hard IP and icetime Support
This commit is contained in:
Clifford Wolf
GitHub
commit
14b44ca866
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@ -1,19 +1,36 @@
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<!DOCTYPE html>
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<html><head><meta charset="UTF-8">
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<style>
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.multitab {
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margin-left: auto;
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vertical-align: top;
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margin-left: auto;
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.ctab td, .ctab th, .cstab th, .cstab td {
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.ctab td {
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.ctab td, .cstab td {
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font-family:monospace;
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}
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</style>
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<title>Project IceStorm – UltraPlus Features Documentation</title>
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</head><body>
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@ -264,4 +281,145 @@ can be used as an open-drain IO using the standard IO cell.</p>
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<tr><td>100kΩ<br/>(default)</td><td>!cf_bit_35<br/>!B6[15]</td><td>!cf_bit_39<br/>!B12[15]</td></tr>
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</table>
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<h2>Hard IP</h2>
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<p>The UltraPlus devices contain three types of Hard IP: I<sup>2</sup>C (<span style="font-family:monospace">SB_I2C</span>), SPI (<span style="font-family:monospace">SB_SPI</span>), and LED PWM generation
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(<span style="font-family:monospace">SB_LEDDA_IP</span>). The connections and configurations for each of these blocks are documented below. Names in italics are parameters rather than actual bits,
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where multiple bits are used to enable an IP they are labeled as <span style="font-family:monospace"><em>_ENABLE_0</em></span>, <span style="font-family:monospace"><em>_ENABLE_1</em></span>, etc. </p>
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<table class="multitab"><tr><td>
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<table class="cstab">
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<tr><th>Signal</th><th>I2C<br/>(0, 31, 0)</th><th>I2C<br/>(25, 31, 0)</th></tr>
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<tr><td>SBACKO</td><td>(0, 30, slf_op_6)</td><td>(25, 30, slf_op_6)</td></tr>
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<tr><td>SBADRI0</td><td>(0, 30, lutff_1/in_0)</td><td>(25, 30, lutff_1/in_0)</td></tr>
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<tr><td>SBADRI1</td><td>(0, 30, lutff_2/in_0)</td><td>(25, 30, lutff_2/in_0)</td></tr>
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<tr><td>SBADRI2</td><td>(0, 30, lutff_3/in_0)</td><td>(25, 30, lutff_3/in_0)</td></tr>
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<tr><td>SBADRI3</td><td>(0, 30, lutff_4/in_0)</td><td>(25, 30, lutff_4/in_0)</td></tr>
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<tr><td>SBADRI4</td><td>(0, 30, lutff_5/in_0)</td><td>(25, 30, lutff_5/in_0)</td></tr>
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<tr><td>SBADRI5</td><td>(0, 30, lutff_6/in_0)</td><td>(25, 30, lutff_6/in_0)</td></tr>
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<tr><td>SBADRI6</td><td>(0, 30, lutff_7/in_0)</td><td>(25, 30, lutff_7/in_0)</td></tr>
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<tr><td>SBADRI7</td><td>(0, 29, lutff_2/in_0)</td><td>(25, 29, lutff_2/in_0)</td></tr>
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<tr><td>SBCLKI</td><td>(0, 30, clk)</td><td>(25, 30, clk)</td></tr>
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<tr><td>SBDATI0</td><td>(0, 29, lutff_5/in_0)</td><td>(25, 29, lutff_5/in_0)</td></tr>
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<tr><td>SBDATI1</td><td>(0, 29, lutff_6/in_0)</td><td>(25, 29, lutff_6/in_0)</td></tr>
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<tr><td>SBDATI2</td><td>(0, 29, lutff_7/in_0)</td><td>(25, 29, lutff_7/in_0)</td></tr>
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<tr><td>SBDATI3</td><td>(0, 30, lutff_0/in_3)</td><td>(25, 30, lutff_0/in_3)</td></tr>
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<tr><td>SBDATI4</td><td>(0, 30, lutff_5/in_1)</td><td>(25, 30, lutff_5/in_1)</td></tr>
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<tr><td>SBDATI5</td><td>(0, 30, lutff_6/in_1)</td><td>(25, 30, lutff_6/in_1)</td></tr>
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<tr><td>SBDATI6</td><td>(0, 30, lutff_7/in_1)</td><td>(25, 30, lutff_7/in_1)</td></tr>
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<tr><td>SBDATI7</td><td>(0, 30, lutff_0/in_0)</td><td>(25, 30, lutff_0/in_0)</td></tr>
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<tr><td>SBDATO0</td><td>(0, 29, slf_op_6)</td><td>(25, 29, slf_op_6)</td></tr>
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<tr><td>SBDATO1</td><td>(0, 29, slf_op_7)</td><td>(25, 29, slf_op_7)</td></tr>
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<tr><td>SBDATO2</td><td>(0, 30, slf_op_0)</td><td>(25, 30, slf_op_0)</td></tr>
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<tr><td>SBDATO3</td><td>(0, 30, slf_op_1)</td><td>(25, 30, slf_op_1)</td></tr>
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<tr><td>SBDATO4</td><td>(0, 30, slf_op_2)</td><td>(25, 30, slf_op_2)</td></tr>
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<tr><td>SBDATO5</td><td>(0, 30, slf_op_3)</td><td>(25, 30, slf_op_3)</td></tr>
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<tr><td>SBDATO6</td><td>(0, 30, slf_op_4)</td><td>(25, 30, slf_op_4)</td></tr>
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<tr><td>SBDATO7</td><td>(0, 30, slf_op_5)</td><td>(25, 30, slf_op_5)</td></tr>
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<tr><td>SBRWI</td><td>(0, 29, lutff_4/in_0)</td><td>(25, 29, lutff_4/in_0)</td></tr>
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<tr><td>SBSTBI</td><td>(0, 29, lutff_3/in_0)</td><td>(25, 29, lutff_3/in_0)</td></tr>
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<tr><td>I2CIRQ</td><td>(0, 30, slf_op_7)</td><td>(25, 30, slf_op_7)</td></tr>
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<tr><td>I2CWKUP</td><td>(0, 29, slf_op_5)</td><td>(25, 29, slf_op_5)</td></tr>
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<tr><td>SCLI</td><td>(0, 29, lutff_2/in_1)</td><td>(25, 29, lutff_2/in_1)</td></tr>
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<tr><td>SCLO</td><td>(0, 29, slf_op_3)</td><td>(25, 29, slf_op_3)</td></tr>
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<tr><td>SCLOE</td><td>(0, 29, slf_op_4)</td><td>(25, 29, slf_op_4)</td></tr>
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<tr><td>SDAI</td><td>(0, 29, lutff_1/in_1)</td><td>(25, 29, lutff_1/in_1)</td></tr>
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<tr><td>SDAO</td><td>(0, 29, slf_op_1)</td><td>(25, 29, slf_op_1)</td></tr>
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<tr><td>SDAOE</td><td>(0, 29, slf_op_2)</td><td>(25, 29, slf_op_2)</td></tr>
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<tr><td><em>I2C_ENABLE_0</em></td><td><em>(13, 31, cbit2usealt_in_0)</em></td><td><em>(19, 31, cbit2usealt_in_0)</em></td></tr>
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<tr><td><em>I2C_ENABLE_1</em></td><td><em>(12, 31, cbit2usealt_in_1)</em></td><td><em>(19, 31, cbit2usealt_in_1)</em></td></tr>
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<tr><td><em>SDA_INPUT_DELAYED</em></td><td><em>(12, 31, SDA_input_delay)</em></td><td><em>(19, 31, SDA_input_delay)</em></td></tr>
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<tr><td><em>SDA_OUTPUT_DELAYED</em></td><td><em>(12, 31, SDA_output_delay)</em></td><td><em>(19, 31, SDA_output_delay)</em></td></tr>
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</table>
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</td><td>
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<table class="cstab">
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<tr><th>Signal</th><th>SPI<br/>(0, 0, 0)</th><th>SPI<br/>(25, 0, 1)</th></tr>
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<tr><td>SBACKO</td><td>(0, 20, slf_op_1)</td><td>(25, 20, slf_op_1)</td></tr>
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<tr><td>SBADRI0</td><td>(0, 19, lutff_1/in_1)</td><td>(25, 19, lutff_1/in_1)</td></tr>
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<tr><td>SBADRI1</td><td>(0, 19, lutff_2/in_1)</td><td>(25, 19, lutff_2/in_1)</td></tr>
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<tr><td>SBADRI2</td><td>(0, 20, lutff_0/in_3)</td><td>(25, 20, lutff_0/in_3)</td></tr>
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<tr><td>SBADRI3</td><td>(0, 20, lutff_1/in_3)</td><td>(25, 20, lutff_1/in_3)</td></tr>
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<tr><td>SBADRI4</td><td>(0, 20, lutff_2/in_3)</td><td>(25, 20, lutff_2/in_3)</td></tr>
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<tr><td>SBADRI5</td><td>(0, 20, lutff_3/in_3)</td><td>(25, 20, lutff_3/in_3)</td></tr>
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<tr><td>SBADRI6</td><td>(0, 20, lutff_4/in_3)</td><td>(25, 20, lutff_4/in_3)</td></tr>
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<tr><td>SBADRI7</td><td>(0, 20, lutff_5/in_3)</td><td>(25, 20, lutff_5/in_3)</td></tr>
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<tr><td>SBCLKI</td><td>(0, 20, clk)</td><td>(25, 20, clk)</td></tr>
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<tr><td>SBDATI0</td><td>(0, 19, lutff_1/in_3)</td><td>(25, 19, lutff_1/in_3)</td></tr>
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<tr><td>SBDATI1</td><td>(0, 19, lutff_2/in_3)</td><td>(25, 19, lutff_2/in_3)</td></tr>
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<tr><td>SBDATI2</td><td>(0, 19, lutff_3/in_3)</td><td>(25, 19, lutff_3/in_3)</td></tr>
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<tr><td>SBDATI3</td><td>(0, 19, lutff_4/in_3)</td><td>(25, 19, lutff_4/in_3)</td></tr>
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<tr><td>SBDATI4</td><td>(0, 19, lutff_5/in_3)</td><td>(25, 19, lutff_5/in_3)</td></tr>
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<tr><td>SBDATI5</td><td>(0, 19, lutff_6/in_3)</td><td>(25, 19, lutff_6/in_3)</td></tr>
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<tr><td>SBDATI6</td><td>(0, 19, lutff_7/in_3)</td><td>(25, 19, lutff_7/in_3)</td></tr>
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<tr><td>SBDATI7</td><td>(0, 19, lutff_0/in_1)</td><td>(25, 19, lutff_0/in_1)</td></tr>
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<tr><td>SBDATO0</td><td>(0, 19, slf_op_1)</td><td>(25, 19, slf_op_1)</td></tr>
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<tr><td>SBDATO1</td><td>(0, 19, slf_op_2)</td><td>(25, 19, slf_op_2)</td></tr>
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<tr><td>SBDATO2</td><td>(0, 19, slf_op_3)</td><td>(25, 19, slf_op_3)</td></tr>
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<tr><td>SBDATO3</td><td>(0, 19, slf_op_4)</td><td>(25, 19, slf_op_4)</td></tr>
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<tr><td>SBDATO4</td><td>(0, 19, slf_op_5)</td><td>(25, 19, slf_op_5)</td></tr>
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<tr><td>SBDATO5</td><td>(0, 19, slf_op_6)</td><td>(25, 19, slf_op_6)</td></tr>
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<tr><td>SBDATO6</td><td>(0, 19, slf_op_7)</td><td>(25, 19, slf_op_7)</td></tr>
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<tr><td>SBDATO7</td><td>(0, 20, slf_op_0)</td><td>(25, 20, slf_op_0)</td></tr>
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<tr><td>SBRWI</td><td>(0, 19, lutff_0/in_3)</td><td>(25, 19, lutff_0/in_3)</td></tr>
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<tr><td>SBSTBI</td><td>(0, 20, lutff_6/in_3)</td><td>(25, 20, lutff_6/in_3)</td></tr>
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<tr><td>MCSNO0</td><td>(0, 21, slf_op_2)</td><td>(25, 21, slf_op_2)</td></tr>
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<tr><td>MCSNO1</td><td>(0, 21, slf_op_4)</td><td>(25, 21, slf_op_4)</td></tr>
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<tr><td>MCSNO2</td><td>(0, 21, slf_op_7)</td><td>(25, 21, slf_op_7)</td></tr>
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<tr><td>MCSNO3</td><td>(0, 22, slf_op_1)</td><td>(25, 22, slf_op_1)</td></tr>
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<tr><td>MCSNOE0</td><td>(0, 21, slf_op_3)</td><td>(25, 21, slf_op_3)</td></tr>
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<tr><td>MCSNOE1</td><td>(0, 21, slf_op_5)</td><td>(25, 21, slf_op_5)</td></tr>
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<tr><td>MCSNOE2</td><td>(0, 22, slf_op_0)</td><td>(25, 22, slf_op_0)</td></tr>
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<tr><td>MCSNOE3</td><td>(0, 22, slf_op_2)</td><td>(25, 22, slf_op_2)</td></tr>
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<tr><td>MI</td><td>(0, 22, lutff_0/in_1)</td><td>(25, 22, lutff_0/in_1)</td></tr>
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<tr><td>MO</td><td>(0, 20, slf_op_6)</td><td>(25, 20, slf_op_6)</td></tr>
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<tr><td>MOE</td><td>(0, 20, slf_op_7)</td><td>(25, 20, slf_op_7)</td></tr>
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<tr><td>SCKI</td><td>(0, 22, lutff_1/in_1)</td><td>(25, 22, lutff_1/in_1)</td></tr>
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<tr><td>SCKO</td><td>(0, 21, slf_op_0)</td><td>(25, 21, slf_op_0)</td></tr>
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<tr><td>SCKOE</td><td>(0, 21, slf_op_1)</td><td>(25, 21, slf_op_1)</td></tr>
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<tr><td>SCSNI</td><td>(0, 22, lutff_2/in_1)</td><td>(25, 22, lutff_2/in_1)</td></tr>
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<tr><td>SI</td><td>(0, 22, lutff_7/in_3)</td><td>(25, 22, lutff_7/in_3)</td></tr>
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<tr><td>SO</td><td>(0, 20, slf_op_4)</td><td>(25, 20, slf_op_4)</td></tr>
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<tr><td>SOE</td><td>(0, 20, slf_op_5)</td><td>(25, 20, slf_op_5)</td></tr>
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<tr><td>SPIIRQ</td><td>(0, 20, slf_op_2)</td><td>(25, 20, slf_op_2)</td></tr>
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<tr><td>SPIWKUP</td><td>(0, 20, slf_op_3)</td><td>(25, 20, slf_op_3)</td></tr>
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</table>
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</td><td>
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<table class="cstab">
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<tr><th>Signal</th><th>LEDDA_IP<br/>(0, 31, 2)</th></tr>
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<tr><td>LEDDADDR0</td><td>(0, 28, lutff_4/in_0)</td></tr>
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<tr><td>LEDDADDR1</td><td>(0, 28, lutff_5/in_0)</td></tr>
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<tr><td>LEDDADDR2</td><td>(0, 28, lutff_6/in_0)</td></tr>
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<tr><td>LEDDADDR3</td><td>(0, 28, lutff_7/in_0)</td></tr>
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<tr><td>LEDDCLK</td><td>(0, 29, clk)</td></tr>
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<tr><td>LEDDCS</td><td>(0, 28, lutff_2/in_0)</td></tr>
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<tr><td>LEDDDAT0</td><td>(0, 28, lutff_2/in_1)</td></tr>
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<tr><td>LEDDDAT1</td><td>(0, 28, lutff_3/in_1)</td></tr>
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<tr><td>LEDDDAT2</td><td>(0, 28, lutff_4/in_1)</td></tr>
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<tr><td>LEDDDAT3</td><td>(0, 28, lutff_5/in_1)</td></tr>
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<tr><td>LEDDDAT4</td><td>(0, 28, lutff_6/in_1)</td></tr>
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<tr><td>LEDDDAT5</td><td>(0, 28, lutff_7/in_1)</td></tr>
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<tr><td>LEDDDAT6</td><td>(0, 28, lutff_0/in_0)</td></tr>
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<tr><td>LEDDDAT7</td><td>(0, 28, lutff_1/in_0)</td></tr>
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<tr><td>LEDDDEN</td><td>(0, 28, lutff_1/in_1)</td></tr>
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<tr><td>LEDDEXE</td><td>(0, 28, lutff_0/in_1)</td></tr>
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<tr><td>LEDDON</td><td>(0, 29, slf_op_0)</td></tr>
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<tr><td>PWMOUT0</td><td>(0, 28, slf_op_4)</td></tr>
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<tr><td>PWMOUT1</td><td>(0, 28, slf_op_5)</td></tr>
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<tr><td>PWMOUT2</td><td>(0, 28, slf_op_6)</td></tr>
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</table>
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</td></tr></table>
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</p>
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<p>The I<sup>2</sup>C "glitch filter" (referred to as <span style="font-family:monospace">SB_FILTER_50NS</span>) is a seperate module from the I<sup>2</sup>C interface IP, with connections as shown below:
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<table class="ctab">
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<tr><th>Signal</th><th>SB_FILTER_50NS<br/>(25, 31, 2)</th><th>SB_FILTER_50NS<br/>(25, 31, 3)</th></tr>
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<tr><td>FILTERIN</td><td>(25, 27, lutff_1/in_0)</td><td>(25, 27, lutff_0/in_0)</td></tr>
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<tr><td>FILTEROUT</td><td>(25, 27, slf_op_2)</td><td>(25, 27, slf_op_1)</td></tr>
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<tr><td>ENABLE_0</td><td>(25, 30, CBIT_2)</td><td>(25, 30, CBIT_5)</td></tr>
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<tr><td>ENABLE_1</td><td>(25, 30, CBIT_3)</td><td>(25, 30, CBIT_6)</td></tr>
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<tr><td>ENABLE_2</td><td>(25, 30, CBIT_4)</td><td>(25, 30, CBIT_7)</td></tr>
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</table>
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</body></html>
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217
icebox/icebox.py
217
icebox/icebox.py
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@ -4728,7 +4728,214 @@ extra_cells_db = {
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"RGB2_CURRENT_5": (0, 30, "CBIT_7"),
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"CURRENT_MODE": (0, 28, "CBIT_4"),
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}
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},
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("I2C", (0, 31, 0)): {
|
||||
"I2CIRQ": (0, 30, "slf_op_7"),
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"I2CWKUP": (0, 29, "slf_op_5"),
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"I2C_ENABLE_0": (13, 31, "cbit2usealt_in_0"),
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||||
"I2C_ENABLE_1": (12, 31, "cbit2usealt_in_1"),
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"SBACKO": (0, 30, "slf_op_6"),
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"SBADRI0": (0, 30, "lutff_1/in_0"),
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"SBADRI1": (0, 30, "lutff_2/in_0"),
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"SBADRI2": (0, 30, "lutff_3/in_0"),
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"SBADRI3": (0, 30, "lutff_4/in_0"),
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"SBADRI4": (0, 30, "lutff_5/in_0"),
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"SBADRI5": (0, 30, "lutff_6/in_0"),
|
||||
"SBADRI6": (0, 30, "lutff_7/in_0"),
|
||||
"SBADRI7": (0, 29, "lutff_2/in_0"),
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||||
"SBCLKI": (0, 30, "clk"),
|
||||
"SBDATI0": (0, 29, "lutff_5/in_0"),
|
||||
"SBDATI1": (0, 29, "lutff_6/in_0"),
|
||||
"SBDATI2": (0, 29, "lutff_7/in_0"),
|
||||
"SBDATI3": (0, 30, "lutff_0/in_3"),
|
||||
"SBDATI4": (0, 30, "lutff_5/in_1"),
|
||||
"SBDATI5": (0, 30, "lutff_6/in_1"),
|
||||
"SBDATI6": (0, 30, "lutff_7/in_1"),
|
||||
"SBDATI7": (0, 30, "lutff_0/in_0"),
|
||||
"SBDATO0": (0, 29, "slf_op_6"),
|
||||
"SBDATO1": (0, 29, "slf_op_7"),
|
||||
"SBDATO2": (0, 30, "slf_op_0"),
|
||||
"SBDATO3": (0, 30, "slf_op_1"),
|
||||
"SBDATO4": (0, 30, "slf_op_2"),
|
||||
"SBDATO5": (0, 30, "slf_op_3"),
|
||||
"SBDATO6": (0, 30, "slf_op_4"),
|
||||
"SBDATO7": (0, 30, "slf_op_5"),
|
||||
"SBRWI": (0, 29, "lutff_4/in_0"),
|
||||
"SBSTBI": (0, 29, "lutff_3/in_0"),
|
||||
"SCLI": (0, 29, "lutff_2/in_1"),
|
||||
"SCLO": (0, 29, "slf_op_3"),
|
||||
"SCLOE": (0, 29, "slf_op_4"),
|
||||
"SDAI": (0, 29, "lutff_1/in_1"),
|
||||
"SDAO": (0, 29, "slf_op_1"),
|
||||
"SDAOE": (0, 29, "slf_op_2"),
|
||||
"SDA_INPUT_DELAYED": (12, 31, "SDA_input_delay"),
|
||||
"SDA_OUTPUT_DELAYED": (12, 31, "SDA_output_delay"),
|
||||
},
|
||||
("I2C", (25, 31, 0)): {
|
||||
"I2CIRQ": (25, 30, "slf_op_7"),
|
||||
"I2CWKUP": (25, 29, "slf_op_5"),
|
||||
"I2C_ENABLE_0": (19, 31, "cbit2usealt_in_0"),
|
||||
"I2C_ENABLE_1": (19, 31, "cbit2usealt_in_1"),
|
||||
"SBACKO": (25, 30, "slf_op_6"),
|
||||
"SBADRI0": (25, 30, "lutff_1/in_0"),
|
||||
"SBADRI1": (25, 30, "lutff_2/in_0"),
|
||||
"SBADRI2": (25, 30, "lutff_3/in_0"),
|
||||
"SBADRI3": (25, 30, "lutff_4/in_0"),
|
||||
"SBADRI4": (25, 30, "lutff_5/in_0"),
|
||||
"SBADRI5": (25, 30, "lutff_6/in_0"),
|
||||
"SBADRI6": (25, 30, "lutff_7/in_0"),
|
||||
"SBADRI7": (25, 29, "lutff_2/in_0"),
|
||||
"SBCLKI": (25, 30, "clk"),
|
||||
"SBDATI0": (25, 29, "lutff_5/in_0"),
|
||||
"SBDATI1": (25, 29, "lutff_6/in_0"),
|
||||
"SBDATI2": (25, 29, "lutff_7/in_0"),
|
||||
"SBDATI3": (25, 30, "lutff_0/in_3"),
|
||||
"SBDATI4": (25, 30, "lutff_5/in_1"),
|
||||
"SBDATI5": (25, 30, "lutff_6/in_1"),
|
||||
"SBDATI6": (25, 30, "lutff_7/in_1"),
|
||||
"SBDATI7": (25, 30, "lutff_0/in_0"),
|
||||
"SBDATO0": (25, 29, "slf_op_6"),
|
||||
"SBDATO1": (25, 29, "slf_op_7"),
|
||||
"SBDATO2": (25, 30, "slf_op_0"),
|
||||
"SBDATO3": (25, 30, "slf_op_1"),
|
||||
"SBDATO4": (25, 30, "slf_op_2"),
|
||||
"SBDATO5": (25, 30, "slf_op_3"),
|
||||
"SBDATO6": (25, 30, "slf_op_4"),
|
||||
"SBDATO7": (25, 30, "slf_op_5"),
|
||||
"SBRWI": (25, 29, "lutff_4/in_0"),
|
||||
"SBSTBI": (25, 29, "lutff_3/in_0"),
|
||||
"SCLI": (25, 29, "lutff_2/in_1"),
|
||||
"SCLO": (25, 29, "slf_op_3"),
|
||||
"SCLOE": (25, 29, "slf_op_4"),
|
||||
"SDAI": (25, 29, "lutff_1/in_1"),
|
||||
"SDAO": (25, 29, "slf_op_1"),
|
||||
"SDAOE": (25, 29, "slf_op_2"),
|
||||
"SDA_INPUT_DELAYED": (19, 31, "SDA_input_delay"),
|
||||
"SDA_OUTPUT_DELAYED": (19, 31, "SDA_output_delay"),
|
||||
},
|
||||
("SPI", (0, 0, 0)): {
|
||||
"MCSNO0": (0, 21, "slf_op_2"),
|
||||
"MCSNO1": (0, 21, "slf_op_4"),
|
||||
"MCSNO2": (0, 21, "slf_op_7"),
|
||||
"MCSNO3": (0, 22, "slf_op_1"),
|
||||
"MCSNOE0": (0, 21, "slf_op_3"),
|
||||
"MCSNOE1": (0, 21, "slf_op_5"),
|
||||
"MCSNOE2": (0, 22, "slf_op_0"),
|
||||
"MCSNOE3": (0, 22, "slf_op_2"),
|
||||
"MI": (0, 22, "lutff_0/in_1"),
|
||||
"MO": (0, 20, "slf_op_6"),
|
||||
"MOE": (0, 20, "slf_op_7"),
|
||||
"SBACKO": (0, 20, "slf_op_1"),
|
||||
"SBADRI0": (0, 19, "lutff_1/in_1"),
|
||||
"SBADRI1": (0, 19, "lutff_2/in_1"),
|
||||
"SBADRI2": (0, 20, "lutff_0/in_3"),
|
||||
"SBADRI3": (0, 20, "lutff_1/in_3"),
|
||||
"SBADRI4": (0, 20, "lutff_2/in_3"),
|
||||
"SBADRI5": (0, 20, "lutff_3/in_3"),
|
||||
"SBADRI6": (0, 20, "lutff_4/in_3"),
|
||||
"SBADRI7": (0, 20, "lutff_5/in_3"),
|
||||
"SBCLKI": (0, 20, "clk"),
|
||||
"SBDATI0": (0, 19, "lutff_1/in_3"),
|
||||
"SBDATI1": (0, 19, "lutff_2/in_3"),
|
||||
"SBDATI2": (0, 19, "lutff_3/in_3"),
|
||||
"SBDATI3": (0, 19, "lutff_4/in_3"),
|
||||
"SBDATI4": (0, 19, "lutff_5/in_3"),
|
||||
"SBDATI5": (0, 19, "lutff_6/in_3"),
|
||||
"SBDATI6": (0, 19, "lutff_7/in_3"),
|
||||
"SBDATI7": (0, 19, "lutff_0/in_1"),
|
||||
"SBDATO0": (0, 19, "slf_op_1"),
|
||||
"SBDATO1": (0, 19, "slf_op_2"),
|
||||
"SBDATO2": (0, 19, "slf_op_3"),
|
||||
"SBDATO3": (0, 19, "slf_op_4"),
|
||||
"SBDATO4": (0, 19, "slf_op_5"),
|
||||
"SBDATO5": (0, 19, "slf_op_6"),
|
||||
"SBDATO6": (0, 19, "slf_op_7"),
|
||||
"SBDATO7": (0, 20, "slf_op_0"),
|
||||
"SBRWI": (0, 19, "lutff_0/in_3"),
|
||||
"SBSTBI": (0, 20, "lutff_6/in_3"),
|
||||
"SCKI": (0, 22, "lutff_1/in_1"),
|
||||
"SCKO": (0, 21, "slf_op_0"),
|
||||
"SCKOE": (0, 21, "slf_op_1"),
|
||||
"SCSNI": (0, 22, "lutff_2/in_1"),
|
||||
"SI": (0, 22, "lutff_7/in_3"),
|
||||
"SO": (0, 20, "slf_op_4"),
|
||||
"SOE": (0, 20, "slf_op_5"),
|
||||
"SPIIRQ": (0, 20, "slf_op_2"),
|
||||
"SPIWKUP": (0, 20, "slf_op_3"),
|
||||
},
|
||||
("SPI", (25, 0, 1)): {
|
||||
"MCSNO0": (25, 21, "slf_op_2"),
|
||||
"MCSNO1": (25, 21, "slf_op_4"),
|
||||
"MCSNO2": (25, 21, "slf_op_7"),
|
||||
"MCSNO3": (25, 22, "slf_op_1"),
|
||||
"MCSNOE0": (25, 21, "slf_op_3"),
|
||||
"MCSNOE1": (25, 21, "slf_op_5"),
|
||||
"MCSNOE2": (25, 22, "slf_op_0"),
|
||||
"MCSNOE3": (25, 22, "slf_op_2"),
|
||||
"MI": (25, 22, "lutff_0/in_1"),
|
||||
"MO": (25, 20, "slf_op_6"),
|
||||
"MOE": (25, 20, "slf_op_7"),
|
||||
"SBACKO": (25, 20, "slf_op_1"),
|
||||
"SBADRI0": (25, 19, "lutff_1/in_1"),
|
||||
"SBADRI1": (25, 19, "lutff_2/in_1"),
|
||||
"SBADRI2": (25, 20, "lutff_0/in_3"),
|
||||
"SBADRI3": (25, 20, "lutff_1/in_3"),
|
||||
"SBADRI4": (25, 20, "lutff_2/in_3"),
|
||||
"SBADRI5": (25, 20, "lutff_3/in_3"),
|
||||
"SBADRI6": (25, 20, "lutff_4/in_3"),
|
||||
"SBADRI7": (25, 20, "lutff_5/in_3"),
|
||||
"SBCLKI": (25, 20, "clk"),
|
||||
"SBDATI0": (25, 19, "lutff_1/in_3"),
|
||||
"SBDATI1": (25, 19, "lutff_2/in_3"),
|
||||
"SBDATI2": (25, 19, "lutff_3/in_3"),
|
||||
"SBDATI3": (25, 19, "lutff_4/in_3"),
|
||||
"SBDATI4": (25, 19, "lutff_5/in_3"),
|
||||
"SBDATI5": (25, 19, "lutff_6/in_3"),
|
||||
"SBDATI6": (25, 19, "lutff_7/in_3"),
|
||||
"SBDATI7": (25, 19, "lutff_0/in_1"),
|
||||
"SBDATO0": (25, 19, "slf_op_1"),
|
||||
"SBDATO1": (25, 19, "slf_op_2"),
|
||||
"SBDATO2": (25, 19, "slf_op_3"),
|
||||
"SBDATO3": (25, 19, "slf_op_4"),
|
||||
"SBDATO4": (25, 19, "slf_op_5"),
|
||||
"SBDATO5": (25, 19, "slf_op_6"),
|
||||
"SBDATO6": (25, 19, "slf_op_7"),
|
||||
"SBDATO7": (25, 20, "slf_op_0"),
|
||||
"SBRWI": (25, 19, "lutff_0/in_3"),
|
||||
"SBSTBI": (25, 20, "lutff_6/in_3"),
|
||||
"SCKI": (25, 22, "lutff_1/in_1"),
|
||||
"SCKO": (25, 21, "slf_op_0"),
|
||||
"SCKOE": (25, 21, "slf_op_1"),
|
||||
"SCSNI": (25, 22, "lutff_2/in_1"),
|
||||
"SI": (25, 22, "lutff_7/in_3"),
|
||||
"SO": (25, 20, "slf_op_4"),
|
||||
"SOE": (25, 20, "slf_op_5"),
|
||||
"SPIIRQ": (25, 20, "slf_op_2"),
|
||||
"SPIWKUP": (25, 20, "slf_op_3"),
|
||||
},
|
||||
("LEDDA_IP", (0, 31, 2)): {
|
||||
"LEDDADDR0": (0, 28, "lutff_4/in_0"),
|
||||
"LEDDADDR1": (0, 28, "lutff_5/in_0"),
|
||||
"LEDDADDR2": (0, 28, "lutff_6/in_0"),
|
||||
"LEDDADDR3": (0, 28, "lutff_7/in_0"),
|
||||
"LEDDCLK": (0, 29, "clk"),
|
||||
"LEDDCS": (0, 28, "lutff_2/in_0"),
|
||||
"LEDDDAT0": (0, 28, "lutff_2/in_1"),
|
||||
"LEDDDAT1": (0, 28, "lutff_3/in_1"),
|
||||
"LEDDDAT2": (0, 28, "lutff_4/in_1"),
|
||||
"LEDDDAT3": (0, 28, "lutff_5/in_1"),
|
||||
"LEDDDAT4": (0, 28, "lutff_6/in_1"),
|
||||
"LEDDDAT5": (0, 28, "lutff_7/in_1"),
|
||||
"LEDDDAT6": (0, 28, "lutff_0/in_0"),
|
||||
"LEDDDAT7": (0, 28, "lutff_1/in_0"),
|
||||
"LEDDDEN": (0, 28, "lutff_1/in_1"),
|
||||
"LEDDEXE": (0, 28, "lutff_0/in_1"),
|
||||
"LEDDON": (0, 29, "slf_op_0"),
|
||||
"PWMOUT0": (0, 28, "slf_op_4"),
|
||||
"PWMOUT1": (0, 28, "slf_op_5"),
|
||||
"PWMOUT2": (0, 28, "slf_op_6"),
|
||||
},
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4816,6 +5023,10 @@ iotile_t_5k_db.append([["B13[10]"], "IoCtrl", "cf_bit_36"])
|
|||
iotile_t_5k_db.append([["B12[10]"], "IoCtrl", "cf_bit_37"])
|
||||
iotile_t_5k_db.append([["B13[15]"], "IoCtrl", "cf_bit_38"])
|
||||
iotile_t_5k_db.append([["B12[15]"], "IoCtrl", "cf_bit_39"])
|
||||
iotile_t_5k_db.append([["B10[3]"], "IpConfig", "cbit2usealt_in_0"])
|
||||
iotile_t_5k_db.append([["B12[2]"], "IpConfig", "cbit2usealt_in_1"])
|
||||
iotile_t_5k_db.append([["B12[3]"], "IpConfig", "SDA_input_delay"])
|
||||
iotile_t_5k_db.append([["B15[3]"], "IpConfig", "SDA_output_delay"])
|
||||
|
||||
iotile_b_5k_db = list(iotile_b_db)
|
||||
iotile_b_5k_db.append([["B14[15]"], "IoCtrl", "padeb_test_1"])
|
||||
|
|
@ -4828,6 +5039,10 @@ iotile_b_5k_db.append([["B13[10]"], "IoCtrl", "cf_bit_36"])
|
|||
iotile_b_5k_db.append([["B12[10]"], "IoCtrl", "cf_bit_37"])
|
||||
iotile_b_5k_db.append([["B13[15]"], "IoCtrl", "cf_bit_38"])
|
||||
iotile_b_5k_db.append([["B12[15]"], "IoCtrl", "cf_bit_39"])
|
||||
iotile_b_5k_db.append([["B10[3]"], "IpConfig", "cbit2usealt_in_0"])
|
||||
iotile_b_5k_db.append([["B12[2]"], "IpConfig", "cbit2usealt_in_1"])
|
||||
iotile_b_5k_db.append([["B12[3]"], "IpConfig", "SDA_input_delay"])
|
||||
iotile_b_5k_db.append([["B15[3]"], "IpConfig", "SDA_output_delay"])
|
||||
|
||||
for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db, dsp0_5k_db, dsp1_5k_db, dsp2_5k_db, dsp3_5k_db, ipcon_5k_db]:
|
||||
for entry in db:
|
||||
|
|
|
|||
|
|
@ -284,8 +284,10 @@ if ic.is_ultra():
|
|||
for dsp_idx in range(4):
|
||||
print_tile_nonrouting_bits("dsp%d" % dsp_idx, list(ic.dsp_tiles[dsp_idx].keys())[0])
|
||||
print_tile_nonrouting_bits("ipcon", list(ic.ipcon_tiles.keys())[0])
|
||||
|
||||
print(".extra_cell 0 0 WARMBOOT")
|
||||
if ic.is_ultra():
|
||||
print(".extra_cell %d 0 WARMBOOT" % ic.max_x)
|
||||
else:
|
||||
print(".extra_cell 0 0 WARMBOOT")
|
||||
for key in sorted(icebox.warmbootinfo_db[ic.device]):
|
||||
print("%s %s" % (key, " ".join([str(k) for k in icebox.warmbootinfo_db[ic.device][key]])))
|
||||
print()
|
||||
|
|
|
|||
|
|
@ -78,6 +78,13 @@ endif
|
|||
diff -U0 cached_ipcon_5k.txt bitdata_ipcon_5k.txt || cp -v bitdata_ipcon_5k.txt cached_ipcon_5k.txt
|
||||
|
||||
timings:
|
||||
ifeq ($(DEVICECLASS),5k)
|
||||
cp tmedges.txt tmedges.tmp
|
||||
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; done
|
||||
sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
|
||||
python3 timings.py -t timings_up5k.txt work_*/*.sdf > timings_up5k.new
|
||||
mv timings_up5k.new timings_up5k.txt
|
||||
else
|
||||
ifeq ($(DEVICECLASS),8k)
|
||||
cp tmedges.txt tmedges.tmp
|
||||
set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
|
||||
|
|
@ -103,14 +110,14 @@ else
|
|||
mv timings_lp1k.new timings_lp1k.txt
|
||||
endif
|
||||
endif
|
||||
|
||||
endif
|
||||
timings_html:
|
||||
python3 timings.py -h tmedges.txt -t timings_hx1k.txt -l "HX1K with default temp/volt settings" > timings_hx1k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_hx8k.txt -l "HX8K with default temp/volt settings" > timings_hx8k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_lp1k.txt -l "LP1K with default temp/volt settings" > timings_lp1k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html
|
||||
python3 timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html
|
||||
|
||||
python3 timings.py -h tmedges.txt -t timings_up5k.txt -l "UP5K with default temp/volt settings" > timings_up5k.html
|
||||
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt cached_dsp0_5k.txt cached_dsp1_5k.txt cached_dsp2_5k.txt cached_dsp3_5k.txt cached_ipcon_5k.txt
|
||||
gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
|
||||
gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
work_ip/
|
||||
*.html
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#!/usr/bin/env python3
|
||||
import ast, sys
|
||||
|
||||
data = ""
|
||||
with open(sys.argv[1], 'r') as f:
|
||||
data = f.read()
|
||||
|
||||
ip_dat = ast.literal_eval("{\n" + data + "}")
|
||||
|
||||
def is_cbit(ident):
|
||||
if "_ENABLE" in ident or "DELAYED" in ident:
|
||||
return True
|
||||
else:
|
||||
return False
|
||||
|
||||
def is_bus(ident):
|
||||
return ident.startswith("SB")
|
||||
|
||||
ips = sorted(ip_dat)
|
||||
print ("<table class=\"cstab\">\n<tr><th>Signal</th>", end='')
|
||||
for ip in ips:
|
||||
t, loc = ip
|
||||
x, y, z = loc
|
||||
print("<th>%s<br/>(%d, %d, %d)</th>" % (t, x, y, z), end='')
|
||||
print ("</tr>")
|
||||
|
||||
# TODO: could group busses?
|
||||
for print_t in ["SB", "G", "CBIT"]:
|
||||
for n in sorted(ip_dat[ips[0]]):
|
||||
if is_bus(n) != (print_t == "SB"):
|
||||
continue
|
||||
if is_cbit(n) != (print_t == "CBIT"):
|
||||
continue
|
||||
print("<tr>", end='')
|
||||
em_o = ""
|
||||
em_c = ""
|
||||
if is_cbit(n):
|
||||
em_o = "<em>"
|
||||
em_c = "</em>"
|
||||
print("<td>%s%s%s</td>" % (em_o, n, em_c), end='')
|
||||
for ip in ips:
|
||||
entry = ip_dat[ip][n]
|
||||
x, y, name = entry
|
||||
print("<td>%s(%d, %d, %s)%s</td>" % (em_o, x, y, name, em_c), end='')
|
||||
print("</tr>")
|
||||
print ("</table>")
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import os, sys, re
|
||||
|
||||
device = "up5k"
|
||||
|
||||
pins = "2 3 4 6 9 10 11 12 13 18 19 20 21 25 26 27 28 31 32 34 35 36 37 38 42 43 44 45 46 47 48".split()
|
||||
|
||||
# This is the master IP reverse engineering script for three similar IPs: I2C, SPI and LEDDA_IP
|
||||
ip_types = ["I2C", "SPI", "LEDDA_IP"]
|
||||
ip_locs = { }
|
||||
ip_locs["I2C"] = [(0, 31, 0), (25, 31, 0)]
|
||||
ip_locs["SPI"] = [(0, 0, 0), (25, 0, 1)]
|
||||
ip_locs["LEDDA_IP"] = [(0, 31, 2)]
|
||||
#spram_locs = [(0, 0, 1)]
|
||||
ip_data = { }
|
||||
|
||||
#signals[x][0] -> inputs, signals[x][1] ->outputs
|
||||
ip_signals = {}
|
||||
ip_signals["I2C"] = [["SBCLKI", "SBRWI", "SBSTBI", "SCLI", "SDAI"],
|
||||
["SBACKO", "I2CIRQ", "I2CWKUP", "SCLO", "SCLOE", "SDAO", "SDAOE"]]
|
||||
ip_signals["SPI"] = [["SBCLKI", "SBRWI", "SBSTBI", "MI", "SI", "SCKI", "SCSNI"],
|
||||
["SBACKO", "SPIIRQ", "SPIWKUP", "SO", "SOE", "MO", "MOE", "SCKO", "SCKOE"]]
|
||||
|
||||
# LEDDRST is missing because it doesn't really exist...
|
||||
ip_signals["LEDDA_IP"] = [["LEDDCS", "LEDDCLK", "LEDDDEN", "LEDDEXE"], ["PWMOUT0", "PWMOUT1", "PWMOUT2", "LEDDON"]]
|
||||
|
||||
fixed_cbits = {}
|
||||
|
||||
fixed_cbits[("I2C", (0, 31, 0))] = ["BUS_ADDR74_0", "I2C_SLAVE_INIT_ADDR_0"]
|
||||
fixed_cbits[("I2C", (25, 31, 0))] = ["BUS_ADDR74_0", "BUS_ADDR74_1", "I2C_SLAVE_INIT_ADDR_1"]
|
||||
|
||||
fixed_cbits[("SPI", (0, 0, 0))] = []
|
||||
fixed_cbits[("SPI", (25, 0, 1))] = ["BUS_ADDR74_1"] # WARNING: this is documented as BUS_ADDR74_0, but this is wrong and will cause icecube to fail. May be the same across devices
|
||||
|
||||
fuzz_cbits = {}
|
||||
fuzz_cbits["I2C"] = ["SDA_INPUT_DELAYED", "SDA_OUTPUT_DELAYED"]
|
||||
|
||||
# Don't add slave address to the list, despite confusing primitive declaration,
|
||||
# it's only set in registers not the bitstream
|
||||
|
||||
#for i in range(2, 10):
|
||||
#fuzz_cbits["I2C"].append("I2C_SLAVE_INIT_ADDR_%d" % i)
|
||||
|
||||
for i in range(8):
|
||||
ip_signals["I2C"][0].append("SBADRI%d" % i)
|
||||
ip_signals["SPI"][0].append("SBADRI%d" % i)
|
||||
for i in range(4):
|
||||
ip_signals["LEDDA_IP"][0].append("LEDDADDR%d" % i)
|
||||
|
||||
for i in range(8):
|
||||
ip_signals["I2C"][0].append("SBDATI%d" % i)
|
||||
ip_signals["SPI"][0].append("SBDATI%d" % i)
|
||||
ip_signals["LEDDA_IP"][0].append("LEDDDAT%d" % i)
|
||||
|
||||
for i in range(8):
|
||||
ip_signals["I2C"][1].append("SBDATO%d" % i)
|
||||
ip_signals["SPI"][1].append("SBDATO%d" % i)
|
||||
|
||||
for i in range(4):
|
||||
ip_signals["SPI"][1].append("MCSNO%d" % i)
|
||||
ip_signals["SPI"][1].append("MCSNOE%d" % i)
|
||||
|
||||
fuzz_net_options = {}
|
||||
fuzz_net_options["I2C"] = ["SBADRI", "SBDATI", "SBDATO"]
|
||||
fuzz_net_options["SPI"] = ["SBADRI", "SBDATI", "SBDATO", "MCSN"]
|
||||
fuzz_net_options["LEDDA_IP"] = ["LEDDADDR", "LEDDDAT"]
|
||||
|
||||
|
||||
available_cbits = {}
|
||||
available_cbits["I2C"] = [("BUS_ADDR74", 4), ("I2C_SLAVE_INIT_ADDR", 10)]
|
||||
available_cbits["SPI"] = [("BUS_ADDR74", 4)]
|
||||
|
||||
# Return a param value in "Lattice style"
|
||||
def get_param_value(param_size, param_name, set_cbits):
|
||||
val = "\"0b"
|
||||
for i in range(param_size):
|
||||
if param_name + "_" + str((param_size - 1) - i) in set_cbits:
|
||||
val += "1"
|
||||
else:
|
||||
val += "0"
|
||||
val += "\""
|
||||
return val
|
||||
|
||||
# Build the output files for a given IP and config, returning
|
||||
# the pin2net map
|
||||
def make_ip(ip_type, ip_loc, fuzz_opt, set_cbits):
|
||||
used_inputs = [ ]
|
||||
used_outputs = [ ]
|
||||
for insig in ip_signals[ip_type][0]:
|
||||
ignore = False
|
||||
for o in fuzz_net_options[ip_type]:
|
||||
if o != fuzz_opt and insig.startswith(o):
|
||||
ignore = True
|
||||
if not ignore:
|
||||
used_inputs.append(insig)
|
||||
for outsig in ip_signals[ip_type][1]:
|
||||
ignore = False
|
||||
for o in fuzz_net_options[ip_type]:
|
||||
if o != fuzz_opt and outsig.startswith(o):
|
||||
ignore = True
|
||||
if not ignore:
|
||||
used_outputs.append(outsig)
|
||||
all_sigs = used_inputs + used_outputs
|
||||
all_cbits = set()
|
||||
all_cbits.update(set_cbits)
|
||||
if (ip_type, ip_loc) in fixed_cbits:
|
||||
all_cbits.update(fixed_cbits[(ip_type, ip_loc)])
|
||||
with open("./work_ip/ip.v", "w") as f:
|
||||
print("module top(", file=f)
|
||||
for s in used_inputs:
|
||||
print("input %s," % s, file=f)
|
||||
for s in used_outputs[:-1]:
|
||||
print("output %s," % s, file=f)
|
||||
print("output %s);" % used_outputs[-1], file=f)
|
||||
print("SB_%s" % ip_type, file=f)
|
||||
if ip_type in available_cbits:
|
||||
print("\t#(", file=f)
|
||||
for p in available_cbits[ip_type]:
|
||||
name, width = p
|
||||
comma = "," if p != available_cbits[ip_type][-1] else ""
|
||||
print("\t\t.%s(%s)%s" % (name, get_param_value(width, name, all_cbits), comma), file=f)
|
||||
print("\t)", file=f)
|
||||
print("\tip_inst (",file=f)
|
||||
for sig in all_sigs[:-1]:
|
||||
print("\t\t.%s(%s)," % (sig, sig), file=f)
|
||||
print("\t\t.%s(%s)" % (all_sigs[-1], all_sigs[-1]), file=f)
|
||||
print("\t)", file=f)
|
||||
if "SDA_INPUT_DELAYED" in all_cbits:
|
||||
print("\t/* synthesis SDA_INPUT_DELAYED=1 */", file=f)
|
||||
else:
|
||||
print("\t/* synthesis SDA_INPUT_DELAYED=0 */", file=f)
|
||||
if "SDA_OUTPUT_DELAYED" in all_cbits:
|
||||
print("\t/* synthesis SDA_OUTPUT_DELAYED=1 */", file=f)
|
||||
else:
|
||||
print("\t/* synthesis SDA_OUTPUT_DELAYED=0 */", file=f)
|
||||
print(";", file=f)
|
||||
print("endmodule", file=f)
|
||||
pin2net = {}
|
||||
with open("./work_ip/ip.pcf","w") as f:
|
||||
temp_pins = list(pins)
|
||||
for sig in all_sigs:
|
||||
if len(temp_pins) == 0:
|
||||
sys.stderr.write("ERROR: no remaining pins to alloc")
|
||||
sys.exit(1)
|
||||
pin = temp_pins.pop()
|
||||
pin2net[pin] = sig
|
||||
print("set_io %s %s" % (sig, pin), file=f)
|
||||
print("set_location ip_inst %d %d %d" % ip_loc, file=f)
|
||||
return pin2net
|
||||
#Parse the output of an icebox vlog file to determine connectivity
|
||||
def parse_vlog(f, pin2net, net_map):
|
||||
current_net = None
|
||||
|
||||
for line in f:
|
||||
m = re.match(r"wire ([a-zA-Z0-9_]+);", line)
|
||||
if m:
|
||||
net = m.group(1)
|
||||
mp = re.match(r"pin_([a-zA-Z0-9]+)", net)
|
||||
if mp:
|
||||
pin = mp.group(1)
|
||||
if pin in pin2net:
|
||||
current_net = pin2net[pin]
|
||||
else:
|
||||
current_net = None
|
||||
else:
|
||||
current_net = None
|
||||
elif current_net is not None:
|
||||
m = re.match(r"// \((\d+), (\d+), '([a-zA-Z0-9_/]+)'\)", line)
|
||||
if m:
|
||||
x = int(m.group(1))
|
||||
y = int(m.group(2))
|
||||
net = m.group(3)
|
||||
if not (net.startswith("sp") or net.startswith("glb") or net.startswith("neigh") or net.startswith("io") or net.startswith("local") or net.startswith("fabout")):
|
||||
net_map[current_net].add((x, y, net))
|
||||
def parse_exp(f):
|
||||
current_x = 0
|
||||
current_y = 0
|
||||
bits = set()
|
||||
for line in f:
|
||||
splitline = line.split(' ')
|
||||
if splitline[0].endswith("_tile"):
|
||||
current_x = int(splitline[1])
|
||||
current_y = int(splitline[2])
|
||||
elif splitline[0] == "IpConfig":
|
||||
bits.add((current_x, current_y, splitline[1].strip()))
|
||||
return bits
|
||||
|
||||
if not os.path.exists("./work_ip"):
|
||||
os.mkdir("./work_ip")
|
||||
for ip in ip_types:
|
||||
ip_data[ip] = {}
|
||||
for loc in ip_locs[ip]:
|
||||
x, y, z = loc
|
||||
net_cbit_map = {}
|
||||
init_cbits = []
|
||||
for sig in ip_signals[ip][0]:
|
||||
net_cbit_map[sig] = set()
|
||||
for sig in ip_signals[ip][1]:
|
||||
net_cbit_map[sig] = set()
|
||||
first = True
|
||||
for state in ["FUZZ_NETS", "FUZZ_CBITS"]:
|
||||
fuzz_options = None
|
||||
if state == "FUZZ_NETS":
|
||||
fuzz_options = fuzz_net_options[ip]
|
||||
else:
|
||||
if ip in fuzz_cbits:
|
||||
fuzz_options = fuzz_cbits[ip]
|
||||
else:
|
||||
fuzz_options = []
|
||||
for n in fuzz_options:
|
||||
print("Fuzzing %s (%d, %d, %d) %s" % (ip, x, y, z, n))
|
||||
fuzz_nets = fuzz_net_options[ip][0]
|
||||
if state == "FUZZ_NETS":
|
||||
fuzz_nets = n
|
||||
set_cbits = set()
|
||||
if state == "FUZZ_CBITS":
|
||||
set_cbits.add(n)
|
||||
pin2net = make_ip(ip, loc, fuzz_nets, set_cbits)
|
||||
retval = os.system("bash ../../icecube.sh -" + device + " ./work_ip/ip.v > ./work_ip/icecube.log 2>&1")
|
||||
if retval != 0:
|
||||
sys.stderr.write('ERROR: icecube returned non-zero error code\n')
|
||||
sys.exit(1)
|
||||
retval = os.system("../../../icebox/icebox_explain.py ./work_ip/ip.asc > ./work_ip/ip.exp")
|
||||
if retval != 0:
|
||||
sys.stderr.write('ERROR: icebox_explain returned non-zero error code\n')
|
||||
sys.exit(1)
|
||||
retval = os.system("../../../icebox/icebox_vlog.py -l ./work_ip/ip.asc > ./work_ip/ip.vlog")
|
||||
if retval != 0:
|
||||
sys.stderr.write('ERROR: icebox_vlog returned non-zero error code\n')
|
||||
sys.exit(1)
|
||||
with open("./work_ip/ip.vlog", "r") as f:
|
||||
parse_vlog(f, pin2net, net_cbit_map)
|
||||
bits = []
|
||||
with open("./work_ip/ip.exp", "r") as f:
|
||||
bits = parse_exp(f)
|
||||
if first:
|
||||
idx = 0
|
||||
for bit in bits:
|
||||
init_cbits.append(bit)
|
||||
if len(bits) == 1:
|
||||
net_cbit_map[ip + "_ENABLE"] = [bit]
|
||||
else:
|
||||
net_cbit_map[ip + "_ENABLE_" + str(idx)] = [bit]
|
||||
idx += 1
|
||||
for bit in init_cbits:
|
||||
if bit not in bits:
|
||||
bx, by, bn = bit
|
||||
print('WARNING: while fuzzing %s (%d, %d, %d) bit (%d, %d, %s) has unknown function (not always set)' %
|
||||
(ip, x, y, z, bx, by, bn))
|
||||
new_bits = []
|
||||
for bit in bits:
|
||||
if bit not in init_cbits:
|
||||
new_bits.append(bit)
|
||||
if state == "FUZZ_NETS" and len(new_bits) != 0:
|
||||
for bit in new_bits:
|
||||
bx, by, bn = bit
|
||||
print('WARNING: while fuzzing %s (%d, %d, %d) bit (%d, %d, %s) has unknown function (not always set)' %
|
||||
(ip, x, y, z, bx, by, bn))
|
||||
elif state == "FUZZ_CBITS":
|
||||
if len(new_bits) == 0:
|
||||
print('WARNING: while fuzzing %s (%d, %d, %d) param %s causes no change' %
|
||||
(ip, x, y, z, n))
|
||||
else:
|
||||
idx = 0
|
||||
for bit in new_bits:
|
||||
if len(new_bits) == 1:
|
||||
net_cbit_map[n] = [bit]
|
||||
else:
|
||||
net_cbit_map[n + "_" + str(idx)] = [bit]
|
||||
idx += 1
|
||||
first = False
|
||||
ip_data[ip][loc] = net_cbit_map
|
||||
|
||||
with open(device + "_" + ip + "_data.txt", "w") as f:
|
||||
for loc in ip_data[ip]:
|
||||
x, y, z = loc
|
||||
print("\t(\"%s\", (%d, %d, %d)): {" % (ip, x, y, z), file=f)
|
||||
data = ip_data[ip][loc]
|
||||
for net in sorted(data):
|
||||
cnets = []
|
||||
for cnet in data[net]:
|
||||
cnets.append("(%d, %d, \"%s\")" % cnet)
|
||||
print("\t\t%s %s, " % (("\"" + net.replace("[","_").replace("]","") + "\":").ljust(24), " ".join(cnets)), file=f)
|
||||
print("\t},", file=f)
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
("I2C", (0, 31, 0)): {
|
||||
"I2CIRQ": (0, 30, "slf_op_7"),
|
||||
"I2CWKUP": (0, 29, "slf_op_5"),
|
||||
"I2C_ENABLE_0": (13, 31, "cbit2usealt_in_0"),
|
||||
"I2C_ENABLE_1": (12, 31, "cbit2usealt_in_1"),
|
||||
"SBACKO": (0, 30, "slf_op_6"),
|
||||
"SBADRI0": (0, 30, "lutff_1/in_0"),
|
||||
"SBADRI1": (0, 30, "lutff_2/in_0"),
|
||||
"SBADRI2": (0, 30, "lutff_3/in_0"),
|
||||
"SBADRI3": (0, 30, "lutff_4/in_0"),
|
||||
"SBADRI4": (0, 30, "lutff_5/in_0"),
|
||||
"SBADRI5": (0, 30, "lutff_6/in_0"),
|
||||
"SBADRI6": (0, 30, "lutff_7/in_0"),
|
||||
"SBADRI7": (0, 29, "lutff_2/in_0"),
|
||||
"SBCLKI": (0, 30, "clk"),
|
||||
"SBDATI0": (0, 29, "lutff_5/in_0"),
|
||||
"SBDATI1": (0, 29, "lutff_6/in_0"),
|
||||
"SBDATI2": (0, 29, "lutff_7/in_0"),
|
||||
"SBDATI3": (0, 30, "lutff_0/in_3"),
|
||||
"SBDATI4": (0, 30, "lutff_5/in_1"),
|
||||
"SBDATI5": (0, 30, "lutff_6/in_1"),
|
||||
"SBDATI6": (0, 30, "lutff_7/in_1"),
|
||||
"SBDATI7": (0, 30, "lutff_0/in_0"),
|
||||
"SBDATO0": (0, 29, "slf_op_6"),
|
||||
"SBDATO1": (0, 29, "slf_op_7"),
|
||||
"SBDATO2": (0, 30, "slf_op_0"),
|
||||
"SBDATO3": (0, 30, "slf_op_1"),
|
||||
"SBDATO4": (0, 30, "slf_op_2"),
|
||||
"SBDATO5": (0, 30, "slf_op_3"),
|
||||
"SBDATO6": (0, 30, "slf_op_4"),
|
||||
"SBDATO7": (0, 30, "slf_op_5"),
|
||||
"SBRWI": (0, 29, "lutff_4/in_0"),
|
||||
"SBSTBI": (0, 29, "lutff_3/in_0"),
|
||||
"SCLI": (0, 29, "lutff_2/in_1"),
|
||||
"SCLO": (0, 29, "slf_op_3"),
|
||||
"SCLOE": (0, 29, "slf_op_4"),
|
||||
"SDAI": (0, 29, "lutff_1/in_1"),
|
||||
"SDAO": (0, 29, "slf_op_1"),
|
||||
"SDAOE": (0, 29, "slf_op_2"),
|
||||
"SDA_INPUT_DELAYED": (12, 31, "SDA_input_delay"),
|
||||
"SDA_OUTPUT_DELAYED": (12, 31, "SDA_output_delay"),
|
||||
},
|
||||
("I2C", (25, 31, 0)): {
|
||||
"I2CIRQ": (25, 30, "slf_op_7"),
|
||||
"I2CWKUP": (25, 29, "slf_op_5"),
|
||||
"I2C_ENABLE_0": (19, 31, "cbit2usealt_in_0"),
|
||||
"I2C_ENABLE_1": (19, 31, "cbit2usealt_in_1"),
|
||||
"SBACKO": (25, 30, "slf_op_6"),
|
||||
"SBADRI0": (25, 30, "lutff_1/in_0"),
|
||||
"SBADRI1": (25, 30, "lutff_2/in_0"),
|
||||
"SBADRI2": (25, 30, "lutff_3/in_0"),
|
||||
"SBADRI3": (25, 30, "lutff_4/in_0"),
|
||||
"SBADRI4": (25, 30, "lutff_5/in_0"),
|
||||
"SBADRI5": (25, 30, "lutff_6/in_0"),
|
||||
"SBADRI6": (25, 30, "lutff_7/in_0"),
|
||||
"SBADRI7": (25, 29, "lutff_2/in_0"),
|
||||
"SBCLKI": (25, 30, "clk"),
|
||||
"SBDATI0": (25, 29, "lutff_5/in_0"),
|
||||
"SBDATI1": (25, 29, "lutff_6/in_0"),
|
||||
"SBDATI2": (25, 29, "lutff_7/in_0"),
|
||||
"SBDATI3": (25, 30, "lutff_0/in_3"),
|
||||
"SBDATI4": (25, 30, "lutff_5/in_1"),
|
||||
"SBDATI5": (25, 30, "lutff_6/in_1"),
|
||||
"SBDATI6": (25, 30, "lutff_7/in_1"),
|
||||
"SBDATI7": (25, 30, "lutff_0/in_0"),
|
||||
"SBDATO0": (25, 29, "slf_op_6"),
|
||||
"SBDATO1": (25, 29, "slf_op_7"),
|
||||
"SBDATO2": (25, 30, "slf_op_0"),
|
||||
"SBDATO3": (25, 30, "slf_op_1"),
|
||||
"SBDATO4": (25, 30, "slf_op_2"),
|
||||
"SBDATO5": (25, 30, "slf_op_3"),
|
||||
"SBDATO6": (25, 30, "slf_op_4"),
|
||||
"SBDATO7": (25, 30, "slf_op_5"),
|
||||
"SBRWI": (25, 29, "lutff_4/in_0"),
|
||||
"SBSTBI": (25, 29, "lutff_3/in_0"),
|
||||
"SCLI": (25, 29, "lutff_2/in_1"),
|
||||
"SCLO": (25, 29, "slf_op_3"),
|
||||
"SCLOE": (25, 29, "slf_op_4"),
|
||||
"SDAI": (25, 29, "lutff_1/in_1"),
|
||||
"SDAO": (25, 29, "slf_op_1"),
|
||||
"SDAOE": (25, 29, "slf_op_2"),
|
||||
"SDA_INPUT_DELAYED": (19, 31, "SDA_input_delay"),
|
||||
"SDA_OUTPUT_DELAYED": (19, 31, "SDA_output_delay"),
|
||||
},
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
("LEDDA_IP", (0, 31, 2)): {
|
||||
"LEDDADDR0": (0, 28, "lutff_4/in_0"),
|
||||
"LEDDADDR1": (0, 28, "lutff_5/in_0"),
|
||||
"LEDDADDR2": (0, 28, "lutff_6/in_0"),
|
||||
"LEDDADDR3": (0, 28, "lutff_7/in_0"),
|
||||
"LEDDCLK": (0, 29, "clk"),
|
||||
"LEDDCS": (0, 28, "lutff_2/in_0"),
|
||||
"LEDDDAT0": (0, 28, "lutff_2/in_1"),
|
||||
"LEDDDAT1": (0, 28, "lutff_3/in_1"),
|
||||
"LEDDDAT2": (0, 28, "lutff_4/in_1"),
|
||||
"LEDDDAT3": (0, 28, "lutff_5/in_1"),
|
||||
"LEDDDAT4": (0, 28, "lutff_6/in_1"),
|
||||
"LEDDDAT5": (0, 28, "lutff_7/in_1"),
|
||||
"LEDDDAT6": (0, 28, "lutff_0/in_0"),
|
||||
"LEDDDAT7": (0, 28, "lutff_1/in_0"),
|
||||
"LEDDDEN": (0, 28, "lutff_1/in_1"),
|
||||
"LEDDEXE": (0, 28, "lutff_0/in_1"),
|
||||
"LEDDON": (0, 29, "slf_op_0"),
|
||||
"PWMOUT0": (0, 28, "slf_op_4"),
|
||||
"PWMOUT1": (0, 28, "slf_op_5"),
|
||||
"PWMOUT2": (0, 28, "slf_op_6"),
|
||||
},
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
("SPI", (0, 0, 0)): {
|
||||
"MCSNO0": (0, 21, "slf_op_2"),
|
||||
"MCSNO1": (0, 21, "slf_op_4"),
|
||||
"MCSNO2": (0, 21, "slf_op_7"),
|
||||
"MCSNO3": (0, 22, "slf_op_1"),
|
||||
"MCSNOE0": (0, 21, "slf_op_3"),
|
||||
"MCSNOE1": (0, 21, "slf_op_5"),
|
||||
"MCSNOE2": (0, 22, "slf_op_0"),
|
||||
"MCSNOE3": (0, 22, "slf_op_2"),
|
||||
"MI": (0, 22, "lutff_0/in_1"),
|
||||
"MO": (0, 20, "slf_op_6"),
|
||||
"MOE": (0, 20, "slf_op_7"),
|
||||
"SBACKO": (0, 20, "slf_op_1"),
|
||||
"SBADRI0": (0, 19, "lutff_1/in_1"),
|
||||
"SBADRI1": (0, 19, "lutff_2/in_1"),
|
||||
"SBADRI2": (0, 20, "lutff_0/in_3"),
|
||||
"SBADRI3": (0, 20, "lutff_1/in_3"),
|
||||
"SBADRI4": (0, 20, "lutff_2/in_3"),
|
||||
"SBADRI5": (0, 20, "lutff_3/in_3"),
|
||||
"SBADRI6": (0, 20, "lutff_4/in_3"),
|
||||
"SBADRI7": (0, 20, "lutff_5/in_3"),
|
||||
"SBCLKI": (0, 20, "clk"),
|
||||
"SBDATI0": (0, 19, "lutff_1/in_3"),
|
||||
"SBDATI1": (0, 19, "lutff_2/in_3"),
|
||||
"SBDATI2": (0, 19, "lutff_3/in_3"),
|
||||
"SBDATI3": (0, 19, "lutff_4/in_3"),
|
||||
"SBDATI4": (0, 19, "lutff_5/in_3"),
|
||||
"SBDATI5": (0, 19, "lutff_6/in_3"),
|
||||
"SBDATI6": (0, 19, "lutff_7/in_3"),
|
||||
"SBDATI7": (0, 19, "lutff_0/in_1"),
|
||||
"SBDATO0": (0, 19, "slf_op_1"),
|
||||
"SBDATO1": (0, 19, "slf_op_2"),
|
||||
"SBDATO2": (0, 19, "slf_op_3"),
|
||||
"SBDATO3": (0, 19, "slf_op_4"),
|
||||
"SBDATO4": (0, 19, "slf_op_5"),
|
||||
"SBDATO5": (0, 19, "slf_op_6"),
|
||||
"SBDATO6": (0, 19, "slf_op_7"),
|
||||
"SBDATO7": (0, 20, "slf_op_0"),
|
||||
"SBRWI": (0, 19, "lutff_0/in_3"),
|
||||
"SBSTBI": (0, 20, "lutff_6/in_3"),
|
||||
"SCKI": (0, 22, "lutff_1/in_1"),
|
||||
"SCKO": (0, 21, "slf_op_0"),
|
||||
"SCKOE": (0, 21, "slf_op_1"),
|
||||
"SCSNI": (0, 22, "lutff_2/in_1"),
|
||||
"SI": (0, 22, "lutff_7/in_3"),
|
||||
"SO": (0, 20, "slf_op_4"),
|
||||
"SOE": (0, 20, "slf_op_5"),
|
||||
"SPIIRQ": (0, 20, "slf_op_2"),
|
||||
"SPIWKUP": (0, 20, "slf_op_3"),
|
||||
},
|
||||
("SPI", (25, 0, 1)): {
|
||||
"MCSNO0": (25, 21, "slf_op_2"),
|
||||
"MCSNO1": (25, 21, "slf_op_4"),
|
||||
"MCSNO2": (25, 21, "slf_op_7"),
|
||||
"MCSNO3": (25, 22, "slf_op_1"),
|
||||
"MCSNOE0": (25, 21, "slf_op_3"),
|
||||
"MCSNOE1": (25, 21, "slf_op_5"),
|
||||
"MCSNOE2": (25, 22, "slf_op_0"),
|
||||
"MCSNOE3": (25, 22, "slf_op_2"),
|
||||
"MI": (25, 22, "lutff_0/in_1"),
|
||||
"MO": (25, 20, "slf_op_6"),
|
||||
"MOE": (25, 20, "slf_op_7"),
|
||||
"SBACKO": (25, 20, "slf_op_1"),
|
||||
"SBADRI0": (25, 19, "lutff_1/in_1"),
|
||||
"SBADRI1": (25, 19, "lutff_2/in_1"),
|
||||
"SBADRI2": (25, 20, "lutff_0/in_3"),
|
||||
"SBADRI3": (25, 20, "lutff_1/in_3"),
|
||||
"SBADRI4": (25, 20, "lutff_2/in_3"),
|
||||
"SBADRI5": (25, 20, "lutff_3/in_3"),
|
||||
"SBADRI6": (25, 20, "lutff_4/in_3"),
|
||||
"SBADRI7": (25, 20, "lutff_5/in_3"),
|
||||
"SBCLKI": (25, 20, "clk"),
|
||||
"SBDATI0": (25, 19, "lutff_1/in_3"),
|
||||
"SBDATI1": (25, 19, "lutff_2/in_3"),
|
||||
"SBDATI2": (25, 19, "lutff_3/in_3"),
|
||||
"SBDATI3": (25, 19, "lutff_4/in_3"),
|
||||
"SBDATI4": (25, 19, "lutff_5/in_3"),
|
||||
"SBDATI5": (25, 19, "lutff_6/in_3"),
|
||||
"SBDATI6": (25, 19, "lutff_7/in_3"),
|
||||
"SBDATI7": (25, 19, "lutff_0/in_1"),
|
||||
"SBDATO0": (25, 19, "slf_op_1"),
|
||||
"SBDATO1": (25, 19, "slf_op_2"),
|
||||
"SBDATO2": (25, 19, "slf_op_3"),
|
||||
"SBDATO3": (25, 19, "slf_op_4"),
|
||||
"SBDATO4": (25, 19, "slf_op_5"),
|
||||
"SBDATO5": (25, 19, "slf_op_6"),
|
||||
"SBDATO6": (25, 19, "slf_op_7"),
|
||||
"SBDATO7": (25, 20, "slf_op_0"),
|
||||
"SBRWI": (25, 19, "lutff_0/in_3"),
|
||||
"SBSTBI": (25, 20, "lutff_6/in_3"),
|
||||
"SCKI": (25, 22, "lutff_1/in_1"),
|
||||
"SCKO": (25, 21, "slf_op_0"),
|
||||
"SCKOE": (25, 21, "slf_op_1"),
|
||||
"SCSNI": (25, 22, "lutff_2/in_1"),
|
||||
"SI": (25, 22, "lutff_7/in_3"),
|
||||
"SO": (25, 20, "slf_op_4"),
|
||||
"SOE": (25, 20, "slf_op_5"),
|
||||
"SPIIRQ": (25, 20, "slf_op_2"),
|
||||
"SPIWKUP": (25, 20, "slf_op_3"),
|
||||
},
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
set_io sbclki 2
|
||||
set_io sbrwi 3
|
||||
set_io sbstbi 4
|
||||
set_io sbadri0 6
|
||||
set_io sbadri1 9
|
||||
set_io sbadri7 10
|
||||
set_io sbdati0 11
|
||||
set_io sbdati1 12
|
||||
set_io sbdati7 13
|
||||
set_io sbdato0 14
|
||||
set_io sbdato1 15
|
||||
set_io sbdato7 16
|
||||
set_io sbacko 17
|
||||
set_io i2cirq 18
|
||||
set_io i2cwkup 19
|
||||
set_io scli 20
|
||||
set_io sdai 21
|
||||
set_io sclo 23
|
||||
set_io scloe 25
|
||||
set_io sdao 26
|
||||
set_io sdaoe 27
|
||||
set_io scli2 28
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
module top (
|
||||
input sbclki, sbrwi, sbstbi,
|
||||
input sbadri0, sbadri1, sbadri7,
|
||||
input sbdati0, sbdati1, sbdati7,
|
||||
output sbdato0, sbdato1, sbdato7,
|
||||
output sbacko, i2cirq, i2cwkup,
|
||||
input scli, sdai, scli2,
|
||||
output sclo, scloe, sdao, sdaoe
|
||||
);
|
||||
|
||||
SB_I2C #(
|
||||
.I2C_SLAVE_INIT_ADDR("0b1111100001"),
|
||||
.BUS_ADDR74("0b0001")
|
||||
) i2c_ip (
|
||||
.SBCLKI(sbclki),
|
||||
.SBRWI(sbrwi),
|
||||
.SBSTBI(sbstbi),
|
||||
|
||||
.SBADRI0(sbadri0),
|
||||
.SBADRI1(sbadri1),
|
||||
.SBADRI7(sbadri7),
|
||||
|
||||
.SBDATI0(sbdati0),
|
||||
.SBDATI1(sbdati1),
|
||||
.SBDATI7(sbdati7),
|
||||
|
||||
.SBDATO0(sbdato0),
|
||||
.SBDATO1(sbdato1),
|
||||
|
||||
.SBACKO(sbacko),
|
||||
.I2CIRQ(i2cirq),
|
||||
.I2CWKUP(i2cwkup),
|
||||
|
||||
.SCLI(scli),
|
||||
.SCLO(sclo),
|
||||
.SCLOE(scloe),
|
||||
|
||||
.SDAI(sdai),
|
||||
.SDAO(sdao),
|
||||
.SDAOE(sdaoe)
|
||||
)
|
||||
/* synthesis SDA_INPUT_DELAYED=0 */
|
||||
/* synthesis SDA_OUTPUT_DELAYED=0 */
|
||||
/* synthesis SCL_INPUT_FILTERED=1 */
|
||||
;
|
||||
|
||||
|
||||
|
||||
SB_I2C #(
|
||||
.I2C_SLAVE_INIT_ADDR("0b1111100010"),
|
||||
.BUS_ADDR74("0b0011")
|
||||
) i2c_ip2 (
|
||||
.SBCLKI(sbclki),
|
||||
.SBRWI(sbrwi),
|
||||
.SBSTBI(sbstbi),
|
||||
|
||||
.SBADRI0(sbadri0),
|
||||
.SBADRI1(sbadri1),
|
||||
.SBADRI7(sbadri7),
|
||||
|
||||
.SBDATI0(sbdati0),
|
||||
.SBDATI1(sbdati1),
|
||||
.SBDATI7(sbdati7),
|
||||
|
||||
.SBDATO7(sbdato7),
|
||||
|
||||
.SCLI(scli2)
|
||||
|
||||
)
|
||||
/* synthesis SDA_INPUT_DELAYED=0 */
|
||||
/* synthesis SDA_OUTPUT_DELAYED=0 */
|
||||
/* synthesis SCL_INPUT_FILTERED=1 */
|
||||
;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
set_io sbclki 2
|
||||
set_io sbrwi 3
|
||||
set_io sbstbi 4
|
||||
set_io sbadri0 6
|
||||
set_io sbadri1 9
|
||||
set_io sbadri7 10
|
||||
set_io sbdati0 11
|
||||
set_io sbdati1 12
|
||||
set_io sbdati7 13
|
||||
set_io sbdato0 14
|
||||
set_io sbdato1 15
|
||||
set_io sbdato7 16
|
||||
set_io sbacko 17
|
||||
set_io i2cirq 18
|
||||
set_io i2cwkup 19
|
||||
set_io scl 20
|
||||
set_io sda 21
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
module top (
|
||||
input sbclki, sbrwi, sbstbi,
|
||||
input sbadri0, sbadri1, sbadri7,
|
||||
input sbdati0, sbdati1, sbdati7,
|
||||
output sbdato0, sbdato1, sbdato7,
|
||||
output sbacko, i2cirq, i2cwkup,
|
||||
inout scl, sda
|
||||
);
|
||||
|
||||
wire scli, sclo, scloe, sdai, sdao, sdaoe;
|
||||
|
||||
SB_I2C #(
|
||||
.I2C_SLAVE_INIT_ADDR("0b1111100010"),
|
||||
.BUS_ADDR74("0b0011")
|
||||
) i2c_ip (
|
||||
.SBCLKI(sbclki),
|
||||
.SBRWI(sbrwi),
|
||||
.SBSTBI(sbstbi),
|
||||
|
||||
.SBADRI0(sbadri0),
|
||||
.SBADRI1(sbadri1),
|
||||
.SBADRI7(sbadri7),
|
||||
|
||||
.SBDATI0(sbdati0),
|
||||
.SBDATI1(sbdati1),
|
||||
.SBDATI7(sbdati7),
|
||||
|
||||
.SBDATO0(sbdato0),
|
||||
.SBDATO1(sbdato1),
|
||||
.SBDATO7(sbdato7),
|
||||
|
||||
.SBACKO(sbacko),
|
||||
.I2CIRQ(i2cirq),
|
||||
.I2CWKUP(i2cwkup),
|
||||
|
||||
.SCLI(scli),
|
||||
.SCLO(sclo),
|
||||
.SCLOE(scloe),
|
||||
|
||||
.SDAI(sdai),
|
||||
.SDAO(sdao),
|
||||
.SDAOE(sdaoe)
|
||||
) /* synthesis SCL_INPUT_FILTERED=1 */;
|
||||
|
||||
SB_IO #(
|
||||
.PIN_TYPE(6'b101001),
|
||||
.PULLUP(1'b1)
|
||||
) scl_io (
|
||||
.PACKAGE_PIN(scl),
|
||||
.OUTPUT_ENABLE(scloe),
|
||||
.D_OUT_0(sclo),
|
||||
.D_IN_0(scli)
|
||||
);
|
||||
|
||||
|
||||
SB_IO #(
|
||||
.PIN_TYPE(6'b101001),
|
||||
.PULLUP(1'b1)
|
||||
) sda_io (
|
||||
.PACKAGE_PIN(sda),
|
||||
.OUTPUT_ENABLE(sdaoe),
|
||||
.D_OUT_0(sdao),
|
||||
.D_IN_0(sdai)
|
||||
);
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,6 @@
|
|||
CEMux.O LogicCell40.ce
|
||||
CEMux.O PRE_IO.CLOCKENABLE
|
||||
CEMux.O SB_MAC16.CE
|
||||
CEMux.O SB_RAM40_4K.RCLKE
|
||||
CEMux.O SB_RAM40_4K.WCLKE
|
||||
CascadeBuf.O CascadeMux.I
|
||||
|
|
@ -27,12 +28,32 @@ CascadeMux.O SB_RAM40_4K.WADDR[6]
|
|||
CascadeMux.O SB_RAM40_4K.WADDR[7]
|
||||
CascadeMux.O SB_RAM40_4K.WADDR[8]
|
||||
CascadeMux.O SB_RAM40_4K.WADDR[9]
|
||||
ClkMux.O DummyBuf.I
|
||||
ClkMux.O INV.I
|
||||
ClkMux.O LogicCell40.clk
|
||||
ClkMux.O PRE_IO.INPUTCLK
|
||||
ClkMux.O PRE_IO.OUTPUTCLK
|
||||
ClkMux.O SB_MAC16.CLK
|
||||
ClkMux.O SB_RAM40_4K.RCLK
|
||||
ClkMux.O SB_RAM40_4K.WCLK
|
||||
ClkMux.O SB_SPRAM256KA.CLOCK
|
||||
DummyBuf.O Odrv4.I
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR0
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR1
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR2
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR3
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDCLK
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDCS
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT0
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT1
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT2
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT3
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT4
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT5
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT6
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT7
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDEN
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDEXE
|
||||
GND.Y LogicCell40.carryin
|
||||
GND.Y LogicCell40.clk
|
||||
GND.Y LogicCell40.in0
|
||||
|
|
@ -41,6 +62,7 @@ GND.Y LogicCell40.in2
|
|||
GND.Y LogicCell40.in3
|
||||
GND.Y LogicCell40.sr
|
||||
GND.Y PRE_IO.DOUT0
|
||||
GND.Y SB_MAC16.CLK
|
||||
GND.Y SB_RAM40_4K.WCLK
|
||||
Glb2LocalMux.O LocalMux.I
|
||||
GlobalMux.O CEMux.I
|
||||
|
|
@ -60,9 +82,89 @@ IO_PAD.DOUT PRE_IO.PADIN
|
|||
IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER
|
||||
IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN
|
||||
InMux.O CascadeMux.I
|
||||
InMux.O DummyBuf.I
|
||||
InMux.O LogicCell40.in0
|
||||
InMux.O LogicCell40.in1
|
||||
InMux.O LogicCell40.in3
|
||||
InMux.O SB_HFOSC.CLKHFEN
|
||||
InMux.O SB_HFOSC.CLKHFPU
|
||||
InMux.O SB_LFOSC.CLKLFEN
|
||||
InMux.O SB_LFOSC.CLKLFPU
|
||||
InMux.O SB_MAC16.ADDSUBBOT
|
||||
InMux.O SB_MAC16.ADDSUBTOP
|
||||
InMux.O SB_MAC16.AHOLD
|
||||
InMux.O SB_MAC16.A[0]
|
||||
InMux.O SB_MAC16.A[10]
|
||||
InMux.O SB_MAC16.A[11]
|
||||
InMux.O SB_MAC16.A[12]
|
||||
InMux.O SB_MAC16.A[13]
|
||||
InMux.O SB_MAC16.A[14]
|
||||
InMux.O SB_MAC16.A[15]
|
||||
InMux.O SB_MAC16.A[1]
|
||||
InMux.O SB_MAC16.A[2]
|
||||
InMux.O SB_MAC16.A[3]
|
||||
InMux.O SB_MAC16.A[4]
|
||||
InMux.O SB_MAC16.A[5]
|
||||
InMux.O SB_MAC16.A[6]
|
||||
InMux.O SB_MAC16.A[7]
|
||||
InMux.O SB_MAC16.A[8]
|
||||
InMux.O SB_MAC16.A[9]
|
||||
InMux.O SB_MAC16.BHOLD
|
||||
InMux.O SB_MAC16.B[0]
|
||||
InMux.O SB_MAC16.B[10]
|
||||
InMux.O SB_MAC16.B[11]
|
||||
InMux.O SB_MAC16.B[12]
|
||||
InMux.O SB_MAC16.B[13]
|
||||
InMux.O SB_MAC16.B[14]
|
||||
InMux.O SB_MAC16.B[15]
|
||||
InMux.O SB_MAC16.B[1]
|
||||
InMux.O SB_MAC16.B[2]
|
||||
InMux.O SB_MAC16.B[3]
|
||||
InMux.O SB_MAC16.B[4]
|
||||
InMux.O SB_MAC16.B[5]
|
||||
InMux.O SB_MAC16.B[6]
|
||||
InMux.O SB_MAC16.B[7]
|
||||
InMux.O SB_MAC16.B[8]
|
||||
InMux.O SB_MAC16.B[9]
|
||||
InMux.O SB_MAC16.CHOLD
|
||||
InMux.O SB_MAC16.CI
|
||||
InMux.O SB_MAC16.C[0]
|
||||
InMux.O SB_MAC16.C[10]
|
||||
InMux.O SB_MAC16.C[11]
|
||||
InMux.O SB_MAC16.C[12]
|
||||
InMux.O SB_MAC16.C[13]
|
||||
InMux.O SB_MAC16.C[14]
|
||||
InMux.O SB_MAC16.C[15]
|
||||
InMux.O SB_MAC16.C[1]
|
||||
InMux.O SB_MAC16.C[2]
|
||||
InMux.O SB_MAC16.C[3]
|
||||
InMux.O SB_MAC16.C[4]
|
||||
InMux.O SB_MAC16.C[5]
|
||||
InMux.O SB_MAC16.C[6]
|
||||
InMux.O SB_MAC16.C[7]
|
||||
InMux.O SB_MAC16.C[8]
|
||||
InMux.O SB_MAC16.C[9]
|
||||
InMux.O SB_MAC16.DHOLD
|
||||
InMux.O SB_MAC16.D[0]
|
||||
InMux.O SB_MAC16.D[10]
|
||||
InMux.O SB_MAC16.D[11]
|
||||
InMux.O SB_MAC16.D[12]
|
||||
InMux.O SB_MAC16.D[13]
|
||||
InMux.O SB_MAC16.D[14]
|
||||
InMux.O SB_MAC16.D[15]
|
||||
InMux.O SB_MAC16.D[1]
|
||||
InMux.O SB_MAC16.D[2]
|
||||
InMux.O SB_MAC16.D[3]
|
||||
InMux.O SB_MAC16.D[4]
|
||||
InMux.O SB_MAC16.D[5]
|
||||
InMux.O SB_MAC16.D[6]
|
||||
InMux.O SB_MAC16.D[7]
|
||||
InMux.O SB_MAC16.D[8]
|
||||
InMux.O SB_MAC16.D[9]
|
||||
InMux.O SB_MAC16.OHOLDBOT
|
||||
InMux.O SB_MAC16.OHOLDTOP
|
||||
InMux.O SB_MAC16.OLOADBOT
|
||||
InMux.O SB_MAC16.OLOADTOP
|
||||
InMux.O SB_RAM40_4K.MASK[0]
|
||||
InMux.O SB_RAM40_4K.MASK[10]
|
||||
InMux.O SB_RAM40_4K.MASK[11]
|
||||
|
|
@ -95,6 +197,50 @@ InMux.O SB_RAM40_4K.WDATA[6]
|
|||
InMux.O SB_RAM40_4K.WDATA[7]
|
||||
InMux.O SB_RAM40_4K.WDATA[8]
|
||||
InMux.O SB_RAM40_4K.WDATA[9]
|
||||
InMux.O SB_RGBA_DRV.CURREN
|
||||
InMux.O SB_RGBA_DRV.RGB0PWM
|
||||
InMux.O SB_RGBA_DRV.RGB1PWM
|
||||
InMux.O SB_RGBA_DRV.RGB2PWM
|
||||
InMux.O SB_RGBA_DRV.RGBLEDEN
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[0]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[10]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[11]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[12]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[13]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[1]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[2]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[3]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[4]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[5]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[6]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[7]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[8]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[9]
|
||||
InMux.O SB_SPRAM256KA.CHIPSELECT
|
||||
InMux.O SB_SPRAM256KA.DATAIN[0]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[10]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[11]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[12]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[13]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[14]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[15]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[1]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[2]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[3]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[4]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[5]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[6]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[7]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[8]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[9]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[0]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[1]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[2]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[3]
|
||||
InMux.O SB_SPRAM256KA.POWEROFF
|
||||
InMux.O SB_SPRAM256KA.SLEEP
|
||||
InMux.O SB_SPRAM256KA.STANDBY
|
||||
InMux.O SB_SPRAM256KA.WREN
|
||||
IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER
|
||||
IoInMux.O PLL40.BYPASS
|
||||
IoInMux.O PLL40.DYNAMICDELAY[0]
|
||||
|
|
@ -271,6 +417,105 @@ PRE_IO.DIN1 Odrv4.I
|
|||
PRE_IO.PADOEN IO_PAD.OE
|
||||
PRE_IO.PADOUT IO_PAD.DIN
|
||||
PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
|
||||
SB_HFOSC.CLKHF GlobalMux.I
|
||||
SB_HFOSC.CLKHF Odrv12.I
|
||||
SB_HFOSC.CLKHF Odrv4.I
|
||||
SB_LEDDA_IP.PWMOUT0 DummyBuf.I
|
||||
SB_LEDDA_IP.PWMOUT1 DummyBuf.I
|
||||
SB_LEDDA_IP.PWMOUT2 DummyBuf.I
|
||||
SB_LFOSC.CLKLF GlobalMux.I
|
||||
SB_LFOSC.CLKLF Odrv12.I
|
||||
SB_MAC16.ACCUMCO SB_MAC16.ACCUMCI
|
||||
SB_MAC16.CO Odrv12.I
|
||||
SB_MAC16.CO Odrv4.I
|
||||
SB_MAC16.O[0] LocalMux.I
|
||||
SB_MAC16.O[0] Odrv12.I
|
||||
SB_MAC16.O[0] Odrv4.I
|
||||
SB_MAC16.O[10] LocalMux.I
|
||||
SB_MAC16.O[10] Odrv12.I
|
||||
SB_MAC16.O[10] Odrv4.I
|
||||
SB_MAC16.O[11] LocalMux.I
|
||||
SB_MAC16.O[11] Odrv12.I
|
||||
SB_MAC16.O[11] Odrv4.I
|
||||
SB_MAC16.O[12] LocalMux.I
|
||||
SB_MAC16.O[12] Odrv12.I
|
||||
SB_MAC16.O[12] Odrv4.I
|
||||
SB_MAC16.O[13] LocalMux.I
|
||||
SB_MAC16.O[13] Odrv12.I
|
||||
SB_MAC16.O[13] Odrv4.I
|
||||
SB_MAC16.O[14] LocalMux.I
|
||||
SB_MAC16.O[14] Odrv12.I
|
||||
SB_MAC16.O[14] Odrv4.I
|
||||
SB_MAC16.O[15] LocalMux.I
|
||||
SB_MAC16.O[15] Odrv12.I
|
||||
SB_MAC16.O[15] Odrv4.I
|
||||
SB_MAC16.O[16] LocalMux.I
|
||||
SB_MAC16.O[16] Odrv12.I
|
||||
SB_MAC16.O[16] Odrv4.I
|
||||
SB_MAC16.O[17] LocalMux.I
|
||||
SB_MAC16.O[17] Odrv12.I
|
||||
SB_MAC16.O[17] Odrv4.I
|
||||
SB_MAC16.O[18] Odrv12.I
|
||||
SB_MAC16.O[18] Odrv4.I
|
||||
SB_MAC16.O[19] Odrv12.I
|
||||
SB_MAC16.O[19] Odrv4.I
|
||||
SB_MAC16.O[1] LocalMux.I
|
||||
SB_MAC16.O[1] Odrv12.I
|
||||
SB_MAC16.O[1] Odrv4.I
|
||||
SB_MAC16.O[20] Odrv12.I
|
||||
SB_MAC16.O[20] Odrv4.I
|
||||
SB_MAC16.O[21] LocalMux.I
|
||||
SB_MAC16.O[21] Odrv12.I
|
||||
SB_MAC16.O[21] Odrv4.I
|
||||
SB_MAC16.O[22] Odrv12.I
|
||||
SB_MAC16.O[22] Odrv4.I
|
||||
SB_MAC16.O[23] LocalMux.I
|
||||
SB_MAC16.O[23] Odrv12.I
|
||||
SB_MAC16.O[23] Odrv4.I
|
||||
SB_MAC16.O[24] LocalMux.I
|
||||
SB_MAC16.O[24] Odrv12.I
|
||||
SB_MAC16.O[24] Odrv4.I
|
||||
SB_MAC16.O[25] LocalMux.I
|
||||
SB_MAC16.O[25] Odrv12.I
|
||||
SB_MAC16.O[25] Odrv4.I
|
||||
SB_MAC16.O[26] Odrv12.I
|
||||
SB_MAC16.O[26] Odrv4.I
|
||||
SB_MAC16.O[27] Odrv12.I
|
||||
SB_MAC16.O[27] Odrv4.I
|
||||
SB_MAC16.O[28] Odrv12.I
|
||||
SB_MAC16.O[28] Odrv4.I
|
||||
SB_MAC16.O[29] Odrv12.I
|
||||
SB_MAC16.O[29] Odrv4.I
|
||||
SB_MAC16.O[2] LocalMux.I
|
||||
SB_MAC16.O[2] Odrv12.I
|
||||
SB_MAC16.O[2] Odrv4.I
|
||||
SB_MAC16.O[30] Odrv12.I
|
||||
SB_MAC16.O[30] Odrv4.I
|
||||
SB_MAC16.O[31] LocalMux.I
|
||||
SB_MAC16.O[31] Odrv12.I
|
||||
SB_MAC16.O[31] Odrv4.I
|
||||
SB_MAC16.O[3] LocalMux.I
|
||||
SB_MAC16.O[3] Odrv12.I
|
||||
SB_MAC16.O[3] Odrv4.I
|
||||
SB_MAC16.O[4] LocalMux.I
|
||||
SB_MAC16.O[4] Odrv12.I
|
||||
SB_MAC16.O[4] Odrv4.I
|
||||
SB_MAC16.O[5] LocalMux.I
|
||||
SB_MAC16.O[5] Odrv12.I
|
||||
SB_MAC16.O[5] Odrv4.I
|
||||
SB_MAC16.O[6] LocalMux.I
|
||||
SB_MAC16.O[6] Odrv12.I
|
||||
SB_MAC16.O[6] Odrv4.I
|
||||
SB_MAC16.O[7] LocalMux.I
|
||||
SB_MAC16.O[7] Odrv12.I
|
||||
SB_MAC16.O[7] Odrv4.I
|
||||
SB_MAC16.O[8] LocalMux.I
|
||||
SB_MAC16.O[8] Odrv12.I
|
||||
SB_MAC16.O[8] Odrv4.I
|
||||
SB_MAC16.O[9] LocalMux.I
|
||||
SB_MAC16.O[9] Odrv12.I
|
||||
SB_MAC16.O[9] Odrv4.I
|
||||
SB_MAC16.SIGNEXTOUT SB_MAC16.SIGNEXTIN
|
||||
SB_PLL40_2F_CORE.LOCK LocalMux.I
|
||||
SB_PLL40_2F_CORE.PLLOUTCOREA LocalMux.I
|
||||
SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I
|
||||
|
|
@ -336,6 +581,10 @@ SB_RAM40_4K.RDATA[9] LocalMux.I
|
|||
SB_RAM40_4K.RDATA[9] Odrv12.I
|
||||
SB_RAM40_4K.RDATA[9] Odrv4.I
|
||||
SRMux.O LogicCell40.sr
|
||||
SRMux.O SB_MAC16.IRSTBOT
|
||||
SRMux.O SB_MAC16.IRSTTOP
|
||||
SRMux.O SB_MAC16.ORSTBOT
|
||||
SRMux.O SB_MAC16.ORSTTOP
|
||||
SRMux.O SB_RAM40_4K.RE
|
||||
SRMux.O SB_RAM40_4K.WE
|
||||
Sp12to4.O IoSpan4Mux.I
|
||||
|
|
@ -610,6 +859,7 @@ Span12Mux_s9_v.O Span12Mux_s11_h.I
|
|||
Span12Mux_s9_v.O Span12Mux_s5_h.I
|
||||
Span12Mux_s9_v.O Span12Mux_s6_v.I
|
||||
Span12Mux_s9_v.O Span12Mux_s7_h.I
|
||||
Span12Mux_s9_v.O Span12Mux_s9_h.I
|
||||
Span12Mux_s9_v.O Span12Mux_v.I
|
||||
Span12Mux_v.O LocalMux.I
|
||||
Span12Mux_v.O Sp12to4.I
|
||||
|
|
|
|||
|
|
@ -9,8 +9,19 @@ hierarchy -generate PRE_IO o:PADOEN o:PADOUT i:PADIN i:CLOCKENABLE o:DIN0 o:DIN1
|
|||
hierarchy -generate *PLL40* i:PACKAGEPIN i:BYPASS i:DYNAMICDELAY i:EXTFEEDBACK i:LATCHINPUTVALUE \
|
||||
o:LOCK o:PLLOUT* i:REFERENCECLK i:RESETB i:SCLK i:SDI o:SDO i:PLLIN
|
||||
hierarchy -generate SB_RAM40_4K o:RDATA i:RADDR i:WADDR i:MASK i:WDATA i:RCLKE i:RCLK i:RE i:WCLKE i:WCLK i:WE
|
||||
hierarchy -generate SB_MAC16 i:CLK i:CE i:C i:A i:B i:D i:AHOLD i:BHOLD i:CHOLD i:DHOLD i:IRSTTOP i:IRSTBOT \
|
||||
i:ORSTTOP i:ORSTBOT i:OLOADTOP i:OLOADBOT i:ADDSUBTOP i:ADDSUBBOT i:OHOLDTOP i:OHOLDBOT i:CI i:ACCUMCI \
|
||||
i:SIGNEXTIN o:O o:CO o:ACCUMCO o:SIGNEXTOUT
|
||||
hierarchy -generate SB_SPRAM256KA i:ADDRESS i:DATAIN i:MASKWREN i:WREN i:CHIPSELECT i:CLOCK i:STANDBY i:SLEEP \
|
||||
i:POWEROFF i:DATAOUT
|
||||
hierarchy -generate SB_RGBA_DRV i:CURREN i:RGBLEDEN i:RGB*PWM o:RGB*
|
||||
hierarchy -generate SB_LFOSC i:CLKLFPU i:CLKLFEN o:CLKLF
|
||||
hierarchy -generate SB_HFOSC i:CLKHFPU i:CLKHFEN o:CLKHF
|
||||
hierarchy -generate SB_LEDDA_IP i:LEDDCS i:LEDDCLK i:LEDDDAT* i:LEDDADDR* i:LEDDDEN i:LEDDEXE i:LEDDRST o:PWMOUT* o:LEDDON
|
||||
|
||||
hierarchy -generate ICE_CARRY_IN_MUX i:*in o:*out
|
||||
hierarchy -generate *Mux* i:I o:O
|
||||
hierarchy -generate DummyBuf i:I o:O
|
||||
hierarchy -generate Odrv* i:I o:O
|
||||
hierarchy -generate Sp12to4 i:I o:O
|
||||
hierarchy -generate INV i:I o:O
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ endif
|
|||
all: icetime$(EXE)
|
||||
|
||||
ifeq ($(EXE),.js)
|
||||
icetime$(EXE): | share/$(CHIPDB_SUBDIR)/chipdb-384.txt share/$(CHIPDB_SUBDIR)/chipdb-1k.txt share/$(CHIPDB_SUBDIR)/chipdb-8k.txt
|
||||
icetime$(EXE): | share/$(CHIPDB_SUBDIR)/chipdb-384.txt share/$(CHIPDB_SUBDIR)/chipdb-1k.txt share/$(CHIPDB_SUBDIR)/chipdb-8k.txt share/$(CHIPDB_SUBDIR)/chipdb-5k.txt
|
||||
|
||||
share/$(CHIPDB_SUBDIR)/chipdb-384.txt: ../icebox/chipdb-384.txt
|
||||
mkdir -p share/$(CHIPDB_SUBDIR)
|
||||
|
|
@ -20,7 +20,9 @@ share/$(CHIPDB_SUBDIR)/chipdb-1k.txt: ../icebox/chipdb-1k.txt
|
|||
share/$(CHIPDB_SUBDIR)/chipdb-8k.txt: ../icebox/chipdb-8k.txt
|
||||
mkdir -p share/$(CHIPDB_SUBDIR)
|
||||
cp $< $@
|
||||
|
||||
share/$(CHIPDB_SUBDIR)/chipdb-5k.txt: ../icebox/chipdb-5k.txt
|
||||
mkdir -p share/$(CHIPDB_SUBDIR)
|
||||
cp $< $@
|
||||
override LDFLAGS += --embed-file share
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -231,7 +231,10 @@ void read_config()
|
|||
config_device = strtok(nullptr, " \t\r\n");
|
||||
} else
|
||||
if (!strcmp(tok, ".io_tile") || !strcmp(tok, ".logic_tile") ||
|
||||
!strcmp(tok, ".ramb_tile") || !strcmp(tok, ".ramt_tile"))
|
||||
!strcmp(tok, ".ramb_tile") || !strcmp(tok, ".ramt_tile") ||
|
||||
!strcmp(tok, ".ipcon_tile") || !strcmp(tok, ".dsp0_tile") ||
|
||||
!strcmp(tok, ".dsp1_tile") || !strcmp(tok, ".dsp2_tile") ||
|
||||
!strcmp(tok, ".dsp3_tile"))
|
||||
{
|
||||
line_nr = 0;
|
||||
tile_x = atoi(strtok(nullptr, " \t\r\n"));
|
||||
|
|
@ -255,6 +258,16 @@ void read_config()
|
|||
config_tile_type.at(tile_x).at(tile_y) = "ramb";
|
||||
if (!strcmp(tok, ".ramt_tile"))
|
||||
config_tile_type.at(tile_x).at(tile_y) = "ramt";
|
||||
if (!strcmp(tok, ".dsp0_tile"))
|
||||
config_tile_type.at(tile_x).at(tile_y) = "dsp0";
|
||||
if (!strcmp(tok, ".dsp1_tile"))
|
||||
config_tile_type.at(tile_x).at(tile_y) = "dsp1";
|
||||
if (!strcmp(tok, ".dsp2_tile"))
|
||||
config_tile_type.at(tile_x).at(tile_y) = "dsp2";
|
||||
if (!strcmp(tok, ".dsp3_tile"))
|
||||
config_tile_type.at(tile_x).at(tile_y) = "dsp3";
|
||||
if (!strcmp(tok, ".ipcon_tile"))
|
||||
config_tile_type.at(tile_x).at(tile_y) = "ipcon";
|
||||
} else
|
||||
if (!strcmp(tok, ".extra_bit")) {
|
||||
int b = atoi(strtok(nullptr, " \t\r\n"));
|
||||
|
|
@ -666,7 +679,9 @@ double get_delay(std::string cell_type, std::string in_port, std::string out_por
|
|||
|
||||
if (device_type == "hx8k")
|
||||
return get_delay_hx8k(cell_type, in_port, out_port);
|
||||
|
||||
|
||||
if (device_type == "up5k")
|
||||
return get_delay_up5k(cell_type, in_port, out_port);
|
||||
fprintf(stderr, "No built-in timing database for '%s' devices!\n", device_type.c_str());
|
||||
exit(1);
|
||||
}
|
||||
|
|
@ -1077,7 +1092,7 @@ std::string make_seg_pre_io(int x, int y, int z)
|
|||
|
||||
std::string make_lc40(int x, int y, int z)
|
||||
{
|
||||
assert(0 < x && 0 < y && 0 <= z && z < 8);
|
||||
assert(0 <= x && 0 < y && 0 <= z && z < 8);
|
||||
|
||||
auto cell = stringf("lc40_%d_%d_%d", x, y, z);
|
||||
|
||||
|
|
@ -1884,7 +1899,7 @@ void help(const char *cmd)
|
|||
printf(" -j <output_file>\n");
|
||||
printf(" write timing report in json format to the file\n");
|
||||
printf("\n");
|
||||
printf(" -d lp384|lp1k|hx1k|lp8k|hx8k\n");
|
||||
printf(" -d lp384|lp1k|hx1k|lp8k|hx8k|up5k\n");
|
||||
printf(" select the device type (default = lp variant)\n");
|
||||
printf("\n");
|
||||
printf(" -C <chipdb-file>\n");
|
||||
|
|
@ -2025,6 +2040,10 @@ int main(int argc, char **argv)
|
|||
if (device_type == "lp8k" || device_type == "hx8k") {
|
||||
if (config_device != "8k")
|
||||
goto device_chip_mismatch;
|
||||
} else
|
||||
if (device_type == "up5k") {
|
||||
if (config_device != "5k")
|
||||
goto device_chip_mismatch;
|
||||
} else {
|
||||
fprintf(stderr, "Error: Invalid device type '%s'.\n", device_type.c_str());
|
||||
exit(1);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ def timings_to_c(chip, f):
|
|||
print(" exit(1);")
|
||||
print("}")
|
||||
|
||||
for db in "lp384 lp1k lp8k hx1k hx8k".split():
|
||||
for db in "lp384 lp1k lp8k hx1k hx8k up5k".split():
|
||||
with open("../icefuzz/timings_%s.txt" % db, "r") as f:
|
||||
timings_to_c(db, f);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue