mirror of https://github.com/YosysHQ/icestorm.git
icetime progress
This commit is contained in:
Clifford Wolf
parent
d939d1b92f
commit
0cfb6eed91
8
Makefile
8
Makefile
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@ -6,7 +6,7 @@ all:
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$(MAKE) -C iceprog
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$(MAKE) -C icemulti
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$(MAKE) -C icepll
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# $(MAKE) -C icetime
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$(MAKE) -C icetime
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clean:
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$(MAKE) -C icebox clean
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@ -14,7 +14,7 @@ clean:
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$(MAKE) -C iceprog clean
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$(MAKE) -C icemulti clean
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$(MAKE) -C icepll clean
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# $(MAKE) -C icetime clean
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$(MAKE) -C icetime clean
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install:
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$(MAKE) -C icebox install
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@ -22,7 +22,7 @@ install:
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$(MAKE) -C iceprog install
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$(MAKE) -C icemulti install
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$(MAKE) -C icepll install
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# $(MAKE) -C icetime install
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$(MAKE) -C icetime install
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uninstall:
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$(MAKE) -C icebox uninstall
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@ -30,7 +30,7 @@ uninstall:
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$(MAKE) -C iceprog uninstall
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$(MAKE) -C icemulti uninstall
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$(MAKE) -C icepll uninstall
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# $(MAKE) -C icetime uninstall
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$(MAKE) -C icetime uninstall
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.PHONY: all clean install uninstall
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@ -1,4 +1,5 @@
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icetime
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timings.inc
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test[0-9]*
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*.d
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*.o
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@ -6,6 +6,12 @@ all: icetime
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icetime: icetime.o
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icetime.o: icetime.cc timings.inc
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timings.inc: timings.py
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python3 timings.py > timings.inc.new
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mv timings.inc.new timings.inc
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install: all
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mkdir -p $(DESTDIR)$(PREFIX)/bin
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cp icetime $(DESTDIR)$(PREFIX)/bin/icetime
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@ -24,7 +30,7 @@ test0 test1 test2 test3 test4 test5 test6 test7 test8 test9: icetime
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yosys $@.ys
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run0 run1 run2 run3 run4 run5 run6 run7 run8 run9: icetime
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./icetime -P tq144 -p $(subst run,test,$@).pcf $(subst run,test,$@).asc $(subst run,test,$@)_out.v
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./icetime -t -P tq144 -p $(subst run,test,$@).pcf $(subst run,test,$@).asc $(subst run,test,$@)_out.v
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show0 show1 show2 show3 show4 show5 show6 show7 show8 show9: icetime
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bash show.sh $(subst show,test,$@)
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@ -35,7 +41,7 @@ test: test0 test1 test2 test3 test4 test5 test6 test7 test8 test9
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show: show0 show1 show2 show3 show4 show5 show6 show7 show8 show9
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clean:
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rm -f icetime *.o *.d
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rm -f icetime timings.inc *.o *.d
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rm -rf test[0-9]*
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-include *.d
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@ -31,6 +31,7 @@
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#define MAX_SPAN_HACK 1
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FILE *fin, *fout;
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bool verbose = false;
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std::string config_device, selected_package;
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std::vector<std::vector<std::string>> config_tile_type;
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@ -460,28 +461,43 @@ void read_chipdb()
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std::pair<int, int>(x, y);
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}
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#if 1
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for (int net : used_nets)
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if (verbose)
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{
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printf("// NET %d:\n", net);
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for (auto seg : net_to_segments[net])
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printf("// SEG %d %d %s\n", seg.x, seg.y, seg.name.c_str());
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for (auto other : net_buffers[net])
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printf("// BUFFER %d %d %d\n", connection_pos[std::pair<int, int>(net, other)].first,
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connection_pos[std::pair<int, int>(net, other)].second, other);
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for (auto other : net_rbuffers[net])
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printf("// RBUFFER %d %d %d\n", connection_pos[std::pair<int, int>(net, other)].first,
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connection_pos[std::pair<int, int>(net, other)].second, other);
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for (auto other : net_routing[net])
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printf("// ROUTE %d %d %d\n", connection_pos[std::pair<int, int>(net, other)].first,
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connection_pos[std::pair<int, int>(net, other)].second, other);
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for (int net : used_nets)
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{
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printf("// NET %d:\n", net);
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for (auto seg : net_to_segments[net])
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printf("// SEG %d %d %s\n", seg.x, seg.y, seg.name.c_str());
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for (auto other : net_buffers[net])
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printf("// BUFFER %d %d %d\n", connection_pos[std::pair<int, int>(net, other)].first,
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connection_pos[std::pair<int, int>(net, other)].second, other);
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for (auto other : net_rbuffers[net])
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printf("// RBUFFER %d %d %d\n", connection_pos[std::pair<int, int>(net, other)].first,
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connection_pos[std::pair<int, int>(net, other)].second, other);
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for (auto other : net_routing[net])
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printf("// ROUTE %d %d %d\n", connection_pos[std::pair<int, int>(net, other)].first,
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connection_pos[std::pair<int, int>(net, other)].second, other);
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}
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}
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#endif
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}
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bool is_primary(std::string cell_name, std::string out_port)
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{
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auto cell_type = netlist_cell_types[cell_name];
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if (cell_type == "SB_RAM40_4K")
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return true;
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if (cell_type == "LogicCell40" && out_port == "lcout")
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{
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// SEQ_MODE = "4'bX...";
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bool dff_enable = netlist_cell_params[cell_name]["SEQ_MODE"][3] == '1';
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return dff_enable;
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}
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if (cell_type == "PRE_IO")
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return true;
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return false;
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}
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@ -556,7 +572,7 @@ const std::set<std::string> &get_inports(std::string cell_type)
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inports_map["ICE_CARRY_IN_MUX"] = { "carryinitin" };
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inports_map["LogicCell40"] = { "clk", "carryin", "in0", "in1", "in2", "in3", "sr", "ce" };
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inports_map["PRE_IO"] = { "INPUTCLK", "OUTPUTCLK", "LATCHINPUTVALUE", "CLOCKENABLE", "OUTPUTENABLE", "DOUT1", "DOUT0" };
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inports_map["PRE_IO"] = { "INPUTCLK", "OUTPUTCLK", "LATCHINPUTVALUE", "CLOCKENABLE", "OUTPUTENABLE", "DOUT1", "DOUT0", "PADIN" };
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inports_map["SB_RAM40_4K"] = { "RCLK", "RCLKE", "RE", "WCLK", "WCLKE", "WE" };
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@ -569,6 +585,8 @@ const std::set<std::string> &get_inports(std::string cell_type)
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inports_map["SB_RAM40_4K"].insert(stringf("RADDR[%d]", i));
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inports_map["SB_RAM40_4K"].insert(stringf("WADDR[%d]", i));
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}
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inports_map["INTERCONN"] = { "I" };
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}
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if (inports_map.count(cell_type) == 0) {
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@ -579,9 +597,21 @@ const std::set<std::string> &get_inports(std::string cell_type)
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return inports_map.at(cell_type);
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}
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#include "timings.inc"
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double get_delay(std::string cell_type, std::string in_port, std::string out_port)
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{
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return 1.0;
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if (cell_type == "INTERCONN")
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return 0;
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if (config_device == "1k")
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return get_delay_1k(cell_type, in_port, out_port);
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if (config_device == "8k")
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return get_delay_8k(cell_type, in_port, out_port);
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fprintf(stderr, "No built-in timing database for '%s' devices!\n", config_device.c_str());
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exit(1);
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}
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struct TimingAnalysis
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@ -589,6 +619,9 @@ struct TimingAnalysis
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// net_driver[<net_name>] = { <cell_name>, <cell_port> }
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std::map<std::string, std::pair<std::string, std::string>> net_driver;
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// net_max_setup[<net_name>] = { <setup_time>, <cell_name>, <cell_port> }
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std::map<std::string, std::tuple<double, std::string, std::string>> net_max_setup;
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// net_max_path_parent[<net_name>] = { <parent_net>, <cell_name>, <inport>, <outport>, <delay> }
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std::map<std::string, std::tuple<std::string, std::string, std::string, std::string, double>> net_max_path_parent;
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@ -609,20 +642,28 @@ struct TimingAnalysis
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auto &driver_cell = net_driver.at(net).first;
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auto &driver_port = net_driver.at(net).second;
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auto &driver_type = netlist_cell_types.at(driver_cell);
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if (is_primary(driver_cell, driver_port)) {
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net_max_path_delay[net] = 0;
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net_max_path_delay[net] = get_delay(driver_type, "*clkedge*", driver_port);
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return 0;
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}
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auto &driver_type = netlist_cell_types.at(driver_cell);
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auto &driver_inputs = get_inports(driver_type);
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for (auto &inport : driver_inputs)
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for (auto &inport : get_inports(driver_type))
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{
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if (inport == "clk" || inport == "INPUTCLK" || inport == "OUTPUTCLK")
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if (inport == "clk" || inport == "INPUTCLK" || inport == "OUTPUTCLK" || inport == "PADIN")
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continue;
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if (driver_type == "LogicCell40" && driver_port == "carryout") {
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if (inport == "in0" || inport == "in3")
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continue;
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}
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if (driver_type == "LogicCell40" && (driver_port == "ltout" || driver_port == "lcout")) {
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if (inport == "carryin")
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continue;
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}
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std::string *in_net = &netlist_cell_ports.at(driver_cell).at(inport);
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while (net_assignments.count(*in_net))
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in_net = &net_assignments.at(*in_net);
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@ -657,8 +698,20 @@ struct TimingAnalysis
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if (net_name == "")
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continue;
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if (get_inports(netlist_cell_types.at(cell_name)).count(port_name))
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auto &cell_type = netlist_cell_types.at(cell_name);
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if (get_inports(cell_type).count(port_name)) {
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std::string n = net_name;
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while (1) {
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double setup_time = get_delay(cell_type, port_name, "*setup*");
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if (setup_time >= std::get<0>(net_max_setup[n]))
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net_max_setup[n] = std::make_tuple(setup_time, cell_name, port_name);
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if (net_assignments.count(n) == 0)
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break;
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n = net_assignments.at(n);
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}
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continue;
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}
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net_driver[net_name] = { cell_name, port_name };
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all_nets.insert(net_name);
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@ -667,7 +720,7 @@ struct TimingAnalysis
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global_max_path_delay = 0;
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for (auto &net : all_nets) {
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double d = calc_net_max_path_delay(net);
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double d = calc_net_max_path_delay(net) + std::get<0>(net_max_setup[net]);
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if (d > global_max_path_delay) {
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global_max_path_delay = d;
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global_max_path_net = net;
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@ -675,18 +728,47 @@ struct TimingAnalysis
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}
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}
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void report()
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void report(std::string n = std::string())
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{
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std::vector<std::string> lines;
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std::set<std::string> visited_nets;
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std::string n = global_max_path_net;
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if (n.empty()) {
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n = global_max_path_net;
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printf("Report for longest path:\n\n");
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} else {
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printf("Requested report for net %s:\n\n", n.c_str());
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}
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if (net_max_path_delay.count(n) == 0) {
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printf("Net not found: %s\n", n.c_str());
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return;
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}
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double delay = net_max_path_delay.at(n);
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int logic_levels = 0;
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bool last_line = true;
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auto &user = net_max_setup[n];
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if (!std::get<1>(user).empty()) {
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lines.push_back(stringf(" %s (%s) %s [setup]: %.3f ns", std::get<1>(user).c_str(),
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netlist_cell_types.at(std::get<1>(user)).c_str(), std::get<2>(user).c_str(), std::get<0>(user)));
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delay += std::get<0>(user);
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}
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while (1)
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{
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if (net_max_path_parent.count(n) == 0) {
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if (net_max_path_parent.count(n) == 0)
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{
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lines.push_back(stringf("%10.3f ns %s", calc_net_max_path_delay(n), n.c_str()));
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auto &driver_cell = net_driver.at(n).first;
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auto &driver_port = net_driver.at(n).second;
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auto &driver_type = netlist_cell_types.at(driver_cell);
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lines.push_back(stringf(" %s (%s) [clkedge] -> %s: %.3f ns", driver_cell.c_str(),
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driver_type.c_str(), driver_port.c_str(), calc_net_max_path_delay(n)));
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break;
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}
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@ -697,8 +779,10 @@ struct TimingAnalysis
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auto &entry = net_max_path_parent.at(n);
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if (last_line || netlist_cell_types.at(std::get<1>(entry)) == "LogicCell40")
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if (last_line || netlist_cell_types.at(std::get<1>(entry)) == "LogicCell40") {
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lines.push_back(stringf("%10.3f ns %s", calc_net_max_path_delay(n), n.c_str()));
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logic_levels++;
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}
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lines.push_back(stringf(" %s (%s) %s -> %s: %.3f ns", std::get<1>(entry).c_str(),
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netlist_cell_types.at(std::get<1>(entry)).c_str(), std::get<2>(entry).c_str(),
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@ -711,6 +795,11 @@ struct TimingAnalysis
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for (int i = int(lines.size())-1; i >= 0; i--)
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printf("%s\n", lines[i].c_str());
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printf("\n");
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printf("Total number of logic levels: %d\n", logic_levels);
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printf("Total path delay: %.2f ns (%.2f MHz)\n", delay, 1000.0 / delay);
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printf("\n");
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}
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};
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@ -1517,27 +1606,28 @@ void make_interconn(const net_segment_t &src, FILE *graph_f)
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worker.build_net_tree(src.net);
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worker.build_seg_tree(src);
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#if 1
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printf("// INTERCONN %d %d %s %d\n", src.x, src.y, src.name.c_str(), src.net);
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std::function<void(int,int)> print_net_tree = [&] (int net, int indent) {
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printf("// %*sNET_TREE %d\n", indent, "", net);
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for (int child : worker.net_tree.at(net))
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print_net_tree(child, indent+2);
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};
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std::function<void(const net_segment_t&,int,bool)> print_seg_tree = [&] (const net_segment_t &seg, int indent, bool chain) {
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printf("// %*sSEG_TREE %d %d %s %d\n", indent, chain ? "`" : "", seg.x, seg.y, seg.name.c_str(), seg.net);
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if (worker.seg_tree.count(seg)) {
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auto &children = worker.seg_tree.at(seg);
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bool child_chain = children.size() == 1;
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for (auto &child : children)
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print_seg_tree(child, child_chain ? (chain ? indent : indent+1) : indent+2, child_chain);
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} else {
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printf("// %*s DEAD_END (!)\n", indent, "");
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}
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};
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print_net_tree(src.net, 2);
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print_seg_tree(src, 2, false);
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#endif
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if (verbose)
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{
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printf("// INTERCONN %d %d %s %d\n", src.x, src.y, src.name.c_str(), src.net);
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std::function<void(int,int)> print_net_tree = [&] (int net, int indent) {
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printf("// %*sNET_TREE %d\n", indent, "", net);
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for (int child : worker.net_tree.at(net))
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print_net_tree(child, indent+2);
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};
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std::function<void(const net_segment_t&,int,bool)> print_seg_tree = [&] (const net_segment_t &seg, int indent, bool chain) {
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printf("// %*sSEG_TREE %d %d %s %d\n", indent, chain ? "`" : "", seg.x, seg.y, seg.name.c_str(), seg.net);
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if (worker.seg_tree.count(seg)) {
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auto &children = worker.seg_tree.at(seg);
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bool child_chain = children.size() == 1;
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for (auto &child : children)
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print_seg_tree(child, child_chain ? (chain ? indent : indent+1) : indent+2, child_chain);
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} else {
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printf("// %*s DEAD_END (!)\n", indent, "");
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}
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};
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print_net_tree(src.net, 2);
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print_seg_tree(src, 2, false);
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}
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for (auto &seg : worker.target_segs) {
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net_assignments[net_name(seg.net)] = seg_name(seg);
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@ -1564,13 +1654,26 @@ void help(const char *cmd)
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printf(" write a graphviz description of the interconnect tree\n");
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printf(" that includes the given net to 'icetime_graph.dot'.\n");
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printf("\n");
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printf(" -t\n");
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printf(" print a timing estimate (based on topological timing\n");
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printf(" analysis)\n");
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printf("\n");
|
||||
printf(" -T <net_name>\n");
|
||||
printf(" print a timing estimate for the specified net\n");
|
||||
printf("\n");
|
||||
printf(" -v\n");
|
||||
printf(" verbose mode (print all interconnect trees)\n");
|
||||
printf("\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
bool print_timing = false;
|
||||
std::vector<std::string> print_timing_nets;
|
||||
|
||||
int opt;
|
||||
while ((opt = getopt(argc, argv, "p:P:g:")) != -1)
|
||||
while ((opt = getopt(argc, argv, "p:P:g:tT:v")) != -1)
|
||||
{
|
||||
switch (opt)
|
||||
{
|
||||
|
|
@ -1584,6 +1687,15 @@ int main(int argc, char **argv)
|
|||
case 'g':
|
||||
graph_nets.insert(atoi(optarg));
|
||||
break;
|
||||
case 't':
|
||||
print_timing = true;
|
||||
break;
|
||||
case 'T':
|
||||
print_timing_nets.push_back(optarg);
|
||||
break;
|
||||
case 'v':
|
||||
verbose = true;
|
||||
break;
|
||||
default:
|
||||
help(argv[0]);
|
||||
}
|
||||
|
|
@ -1595,7 +1707,7 @@ int main(int argc, char **argv)
|
|||
perror("Can't open input file");
|
||||
exit(1);
|
||||
}
|
||||
fout = stdout;
|
||||
fout = nullptr;
|
||||
} else
|
||||
if (optind+2 == argc) {
|
||||
fin = fopen(argv[optind], "r");
|
||||
|
|
@ -1603,10 +1715,14 @@ int main(int argc, char **argv)
|
|||
perror("Can't open input file");
|
||||
exit(1);
|
||||
}
|
||||
fout = fopen(argv[optind+1], "w");
|
||||
if (fout == nullptr) {
|
||||
perror("Can't open output file");
|
||||
exit(1);
|
||||
if (std::string(argv[optind+1]) == "-") {
|
||||
fout = stdout;
|
||||
} else {
|
||||
fout = fopen(argv[optind+1], "w");
|
||||
if (fout == nullptr) {
|
||||
perror("Can't open output file");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
} else
|
||||
help(argv[0]);
|
||||
|
|
@ -1731,84 +1847,102 @@ int main(int argc, char **argv)
|
|||
extra_wires.insert(port.second);
|
||||
}
|
||||
|
||||
fprintf(fout, "module chip (");
|
||||
const char *io_sep = "";
|
||||
for (auto io : io_names) {
|
||||
fprintf(fout, "%s%s", io_sep, io.c_str());
|
||||
io_sep = ", ";
|
||||
}
|
||||
fprintf(fout, ");\n");
|
||||
|
||||
for (int net : declared_nets)
|
||||
fprintf(fout, " wire net_%d;\n", net);
|
||||
|
||||
for (auto net : extra_wires)
|
||||
fprintf(fout, " wire %s;\n", net.c_str());
|
||||
|
||||
for (auto &it : net_assignments)
|
||||
fprintf(fout, " assign %s = %s;\n", it.first.c_str(), it.second.c_str());
|
||||
|
||||
fprintf(fout, " wire gnd, vcc;\n");
|
||||
fprintf(fout, " GND gnd_cell (.Y(gnd));\n");
|
||||
fprintf(fout, " VCC vcc_cell (.Y(vcc));\n");
|
||||
|
||||
for (auto &str : extra_vlog)
|
||||
fprintf(fout, "%s", str.c_str());
|
||||
|
||||
for (auto it : netlist_cell_types)
|
||||
if (fout != NULL)
|
||||
{
|
||||
const char *sep = "";
|
||||
fprintf(fout, " %s ", it.second.c_str());
|
||||
if (netlist_cell_params.count(it.first)) {
|
||||
fprintf(fout, "#(");
|
||||
for (auto port : netlist_cell_params[it.first]) {
|
||||
fprintf(fout, "module chip (");
|
||||
const char *io_sep = "";
|
||||
for (auto io : io_names) {
|
||||
fprintf(fout, "%s%s", io_sep, io.c_str());
|
||||
io_sep = ", ";
|
||||
}
|
||||
fprintf(fout, ");\n");
|
||||
|
||||
for (int net : declared_nets)
|
||||
fprintf(fout, " wire net_%d;\n", net);
|
||||
|
||||
for (auto net : extra_wires)
|
||||
fprintf(fout, " wire %s;\n", net.c_str());
|
||||
|
||||
for (auto &it : net_assignments)
|
||||
fprintf(fout, " assign %s = %s;\n", it.first.c_str(), it.second.c_str());
|
||||
|
||||
fprintf(fout, " wire gnd, vcc;\n");
|
||||
fprintf(fout, " GND gnd_cell (.Y(gnd));\n");
|
||||
fprintf(fout, " VCC vcc_cell (.Y(vcc));\n");
|
||||
|
||||
for (auto &str : extra_vlog)
|
||||
fprintf(fout, "%s", str.c_str());
|
||||
|
||||
for (auto it : netlist_cell_types)
|
||||
{
|
||||
const char *sep = "";
|
||||
fprintf(fout, " %s ", it.second.c_str());
|
||||
if (netlist_cell_params.count(it.first)) {
|
||||
fprintf(fout, "#(");
|
||||
for (auto port : netlist_cell_params[it.first]) {
|
||||
fprintf(fout, "%s\n .%s(%s)", sep, port.first.c_str(), port.second.c_str());
|
||||
sep = ",";
|
||||
}
|
||||
fprintf(fout, "\n ) ");
|
||||
sep = "";
|
||||
}
|
||||
|
||||
fprintf(fout, "%s (", it.first.c_str());
|
||||
std::map<std::string, std::vector<std::string>> multibit_ports;
|
||||
|
||||
for (auto port : netlist_cell_ports[it.first])
|
||||
{
|
||||
size_t open_bracket_pos = port.first.find('[');
|
||||
if (open_bracket_pos != std::string::npos) {
|
||||
std::string base_name = port.first.substr(0, open_bracket_pos);
|
||||
int bit_index = atoi(port.first.substr(open_bracket_pos+1).c_str());
|
||||
if (multibit_ports[base_name].size() <= bit_index)
|
||||
multibit_ports[base_name].resize(bit_index+1);
|
||||
multibit_ports[base_name][bit_index] = port.second;
|
||||
continue;
|
||||
}
|
||||
|
||||
fprintf(fout, "%s\n .%s(%s)", sep, port.first.c_str(), port.second.c_str());
|
||||
sep = ",";
|
||||
}
|
||||
fprintf(fout, "\n ) ");
|
||||
sep = "";
|
||||
}
|
||||
|
||||
fprintf(fout, "%s (", it.first.c_str());
|
||||
std::map<std::string, std::vector<std::string>> multibit_ports;
|
||||
for (auto it : multibit_ports)
|
||||
{
|
||||
fprintf(fout, "%s\n .%s({", sep, it.first.c_str());
|
||||
sep = ",";
|
||||
|
||||
for (auto port : netlist_cell_ports[it.first])
|
||||
{
|
||||
size_t open_bracket_pos = port.first.find('[');
|
||||
if (open_bracket_pos != std::string::npos) {
|
||||
std::string base_name = port.first.substr(0, open_bracket_pos);
|
||||
int bit_index = atoi(port.first.substr(open_bracket_pos+1).c_str());
|
||||
if (multibit_ports[base_name].size() <= bit_index)
|
||||
multibit_ports[base_name].resize(bit_index+1);
|
||||
multibit_ports[base_name][bit_index] = port.second;
|
||||
continue;
|
||||
const char *sepsep = "";
|
||||
for (int i = int(it.second.size())-1; i >= 0; i--) {
|
||||
std::string wire_name = it.second[i];
|
||||
fprintf(fout, "%s%s", sepsep, wire_name.c_str());
|
||||
sepsep = ", ";
|
||||
}
|
||||
fprintf(fout, "})");
|
||||
}
|
||||
|
||||
fprintf(fout, "%s\n .%s(%s)", sep, port.first.c_str(), port.second.c_str());
|
||||
sep = ",";
|
||||
fprintf(fout, "\n );\n");
|
||||
}
|
||||
|
||||
for (auto it : multibit_ports)
|
||||
{
|
||||
fprintf(fout, "%s\n .%s({", sep, it.first.c_str());
|
||||
sep = ",";
|
||||
|
||||
const char *sepsep = "";
|
||||
for (int i = int(it.second.size())-1; i >= 0; i--) {
|
||||
std::string wire_name = it.second[i];
|
||||
fprintf(fout, "%s%s", sepsep, wire_name.c_str());
|
||||
sepsep = ", ";
|
||||
}
|
||||
fprintf(fout, "})");
|
||||
}
|
||||
|
||||
fprintf(fout, "\n );\n");
|
||||
fprintf(fout, "endmodule\n");
|
||||
}
|
||||
|
||||
fprintf(fout, "endmodule\n");
|
||||
if (print_timing || !print_timing_nets.empty())
|
||||
{
|
||||
printf("\n");
|
||||
printf("icetime topological timing analysis report\n");
|
||||
printf("==========================================\n");
|
||||
printf("\n");
|
||||
|
||||
TimingAnalysis ta;
|
||||
ta.report();
|
||||
TimingAnalysis ta;
|
||||
for (auto &n : print_timing_nets)
|
||||
ta.report(n);
|
||||
ta.report();
|
||||
}
|
||||
else
|
||||
{
|
||||
TimingAnalysis ta;
|
||||
printf("// Timing estimate: %.2f ns (%.2f MHz)\n", ta.global_max_path_delay, 1000.0 / ta.global_max_path_delay);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -148,6 +148,7 @@ with open("%s.ys" % sys.argv[1], "w") as f:
|
|||
print("equiv_status -assert", file=f)
|
||||
|
||||
assert os.system("bash ../icefuzz/icecube.sh %s.v" % sys.argv[1]) == 0
|
||||
os.rename("%s.tmp/outputs/netlist/top_timing.rpt" % sys.argv[1], "%s.rpt" % sys.argv[1])
|
||||
os.rename("%s.v" % sys.argv[1], "%s_in.v" % sys.argv[1])
|
||||
|
||||
if False:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import re
|
||||
|
||||
print("// auto-generated by timings.py from ../icefuzz/timings_*.txt")
|
||||
|
||||
def timings_to_c(chip, f):
|
||||
print("")
|
||||
print("double get_delay_%s(std::string cell_type, std::string in_port, std::string out_port)" % chip)
|
||||
print("{")
|
||||
|
||||
in_cell = False
|
||||
|
||||
for line in f:
|
||||
fields = line.split()
|
||||
if len(fields) == 0:
|
||||
continue
|
||||
|
||||
if fields[0] == "CELL":
|
||||
if in_cell:
|
||||
print(" }")
|
||||
print(" if (cell_type == \"%s\") {" % fields[1])
|
||||
in_cell = True
|
||||
|
||||
if fields[0] == "SETUP":
|
||||
inport = fields[1].split(":")[1]
|
||||
delay = max([0 if s == "*" else float(s) / 1000 for s in fields[3].split(":")])
|
||||
print(" if (in_port == \"%s\" && out_port == \"*setup*\") return %.5f;" % (inport, delay))
|
||||
|
||||
if fields[0] == "IOPATH":
|
||||
if fields[1].startswith("posedge:") or fields[1].startswith("negedge:"):
|
||||
fields[1] = "*clkedge*"
|
||||
delay = max([0 if s == "*" else float(s) / 1000 for s in fields[3].split(":") + fields[4].split(":")])
|
||||
print(" if (in_port == \"%s\" && out_port == \"%s\") return %.5f;" % (fields[1], fields[2], delay))
|
||||
|
||||
|
||||
if in_cell:
|
||||
print(" }")
|
||||
print(" if (in_port == \"*clkedge*\"|| out_port == \"*setup*\") return 0;")
|
||||
print(" fprintf(stderr, \"Unable to resolve delay for path %s -> %s in cell type %s!\\n\", in_port.c_str(), out_port.c_str(), cell_type.c_str());")
|
||||
print(" exit(1);")
|
||||
print("}")
|
||||
|
||||
with open("../icefuzz/timings_1k.txt", "r") as f:
|
||||
timings_to_c("1k", f);
|
||||
|
||||
with open("../icefuzz/timings_8k.txt", "r") as f:
|
||||
timings_to_c("8k", f);
|
||||
|
||||
Loading…
Reference in New Issue