mirror of https://github.com/YosysHQ/icestorm.git
Add -n <module_name> option
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parent
535fde6361
commit
07b9ea6d58
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@ -52,6 +52,9 @@ void help(const char *cmd)
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printf(" -m\n");
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printf(" Save PLL configuration as Verilog module (use with -f)\n");
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printf("\n");
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printf(" -n <module name>\n");
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printf(" Specify different Verilog module name than the default 'pll'\n");
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printf("\n");
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printf(" -q\n");
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printf(" Do not print PLL configuration to stdout\n");
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printf("\n");
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@ -64,11 +67,12 @@ int main(int argc, char **argv)
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double f_pllout = 60;
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bool simple_feedback = true;
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char* filename = NULL;
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char* module_name = NULL;
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bool save_as_module = false;
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bool quiet = false;
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int opt;
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while ((opt = getopt(argc, argv, "i:o:Smf:q")) != -1)
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while ((opt = getopt(argc, argv, "i:o:Smf:n:q")) != -1)
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{
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switch (opt)
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{
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@ -87,6 +91,9 @@ int main(int argc, char **argv)
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case 'f':
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filename = optarg;
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break;
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case 'n':
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module_name = optarg;
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break;
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case 'q':
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quiet = true;
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break;
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@ -238,11 +245,11 @@ int main(int argc, char **argv)
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f_pllin, f_pllout, best_fout);
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// generate Verilog module
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fprintf(f, "module pll(\n"
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fprintf(f, "module %s(\n"
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"\tinput clock_in,\n"
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"\toutput clock_out,\n"
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"\toutput locked\n"
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"\t);\n\n"
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"\t);\n\n", (module_name ? module_name : "pll")
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);
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// save iCE40 PLL tile configuration
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