mirror of https://github.com/YosysHQ/icestorm.git
Import of icestorm-snapshot-150401.zip
This commit is contained in:
Clifford Wolf
parent
dfeb92a46b
commit
0347c37d56
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@ -27,10 +27,12 @@ class iceconfig:
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def clear(self):
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self.max_x = 0
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self.max_y = 0
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self.device = ""
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self.logic_tiles = dict()
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self.io_tiles = dict()
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self.ram_tiles = dict()
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self.ram_init = dict()
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self.extra_bits = set()
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def setup_empty_1k(self):
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self.clear()
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@ -52,6 +54,12 @@ class iceconfig:
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self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)]
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self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)]
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def lookup_extra_bit(self, bit):
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assert self.device in extra_bits_db
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if bit in extra_bits_db[self.device]:
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return extra_bits_db[self.device][bit]
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return ("UNKNOWN_FUNCTION",)
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def tile(self, x, y):
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if (x, y) in self.io_tiles: return self.io_tiles[(x, y)]
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if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)]
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@ -354,6 +362,8 @@ class iceconfig:
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assert expected_data_lines == 0
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continue
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if line[0][0] != ".":
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if expected_data_lines == -1:
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continue
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if line[0][0] != "0" and line[0][0] != "1":
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print("%sWarning: ignoring data block in line %d: %s" % (logprefix, linenum, linetext.strip()))
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expected_data_lines = 0
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@ -362,7 +372,7 @@ class iceconfig:
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current_data.append(line[0])
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expected_data_lines -= 1
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continue
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assert expected_data_lines == 0
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assert expected_data_lines <= 0
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if line[0] in (".io_tile", ".logic_tile", ".ram_tile"):
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current_data = list()
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expected_data_lines = 16
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@ -377,8 +387,15 @@ class iceconfig:
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if line[0] == ".ram_tile":
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self.ram_tiles[(int(line[1]), int(line[2]))] = current_data
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continue
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if line[0] == ".extra_bit":
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self.extra_bits.add((int(line[1]), int(line[2]), int(line[3])))
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continue
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if line[0] == ".device":
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assert line[1] == "1k"
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assert line[1] in ["1k"]
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self.device = line[1]
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continue
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if line[0] == ".comment":
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expected_data_lines = -1
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continue
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print("%sWarning: ignoring line %d: %s" % (logprefix, linenum, linetext.strip()))
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@ -770,6 +787,12 @@ def parse_db(text):
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db.append(line)
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return db
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extra_bits_db = {
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"1k": {
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(0, 331, 142): ("routing", "padin_1", "glb_netwk_1")
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}
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}
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iotile_full_db = parse_db(iceboxdb.database_io_txt)
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logictile_db = parse_db(iceboxdb.database_logic_txt)
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ramtile_db = parse_db(iceboxdb.database_ram_txt)
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@ -153,5 +153,11 @@ for idx in ic.logic_tiles:
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for idx in ic.ram_tiles:
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print_tile(".ram_tile %d %d" % idx, ic, idx[0], idx[1], ic.ram_tiles[idx], ic.tile_db(idx[0], idx[1]))
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for bit in ic.extra_bits:
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print()
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print(".extra_bit %d %d %d" % bit)
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print(" ".join(ic.lookup_extra_bit(bit)))
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print()
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@ -1,25 +1,29 @@
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CC = clang
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CXX = clang
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LDFLAGS = -lm -lstdc++
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CFLAGS = -MD -Os -Wall -std=c99
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CXXFLAGS = -MD -Os -Wall -std=c99
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LDLIBS = -lm -lstdc++
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CXXFLAGS = -MD -O0 -ggdb -Wall -std=c++11
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all: iceunpack
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all: icepack iceunpack
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iceunpack: iceunpack.o
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icepack: icepack.o
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iceunpack: icepack
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ln -sf icepack iceunpack
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install: all
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cp iceunpack /usr/local/bin/iceunpack
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cp icepack /usr/local/bin/icepack
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ln -s icepack /usr/local/bin/iceunpack
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uninstall:
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rm -f /usr/local/bin/icepack
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rm -f /usr/local/bin/iceunpack
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clean:
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rm -f icepack
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rm -f iceunpack
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rm -f *.o *.d
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-include *.d
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.PHONY: install uninstall clean
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.PHONY: all install uninstall clean
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File diff suppressed because it is too large
Load Diff
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@ -1,368 +0,0 @@
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// Written by Mathias Lasser
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// License terms are unclear at the moment
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#include<stdio.h>
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#include<stdbool.h>
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#include<stdlib.h>
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#include<stdint.h>
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#include<string.h>
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int enable_debug=0;
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#define debugf(...) do{if(enable_debug)fprintf(stderr,__VA_ARGS__);}while(0)
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#pragma pack(2)
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typedef struct
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{
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uint16_t bfType;
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uint32_t bfSize;
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uint16_t bfReserved1;
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uint16_t bfReserved2;
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uint32_t bfOffBits;
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}BITMAPFILEHEADER;
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typedef struct
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{
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uint32_t biSize;
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uint32_t biWidth;
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uint32_t biHeight;
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uint16_t biPlanes;
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uint16_t biBitCount;
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uint32_t biCompression;
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uint32_t biSizeImage;
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uint32_t biXPelsPerMeter;
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uint32_t biYPelsPerMeter;
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uint32_t biClrUsed;
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uint32_t biClrImportant;
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}BITMAPINFOHEADER;
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typedef struct{
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uint16_t boot_mode;
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uint16_t crc;
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uint8_t freq;
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uint8_t bank;
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uint32_t write_pointer;
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uint32_t CRAM_rowsize;
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uint32_t CRAM_colsize;
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uint8_t* CRAM[4];
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uint32_t BRAM_rowsize;
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uint32_t BRAM_colsize;
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uint8_t* BRAM[4];
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}FPGA_t;
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typedef struct{
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uint32_t len;
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uint32_t pointer;
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uint16_t crc;
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uint8_t payload[0];
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}bitstream_t;
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typedef union{
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struct{
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uint8_t lo:4;
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uint8_t hi:4;
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};
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uint8_t full;
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}nibble_t;
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const char* freq_settings[]={"low","medium","high"};
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const char* boot_settings[]={"Disable","Enable"};
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uint16_t crc16(uint32_t crc,uint8_t in){
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for(int i=7;i>=0;i--){
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crc<<=1;
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if((crc^(in<<(16-i)))&0x10000)
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crc^=0x1021;
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}
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return crc;
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}
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uint32_t get_byte(bitstream_t* bitstream){
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if(bitstream->pointer>=bitstream->len)return 0xFFFFFF;
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uint8_t data=bitstream->payload[bitstream->pointer++];
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bitstream->crc=crc16(bitstream->crc,data);
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return data;
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}
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uint32_t get_payload(bitstream_t* bitstream,int len){
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uint32_t ret=get_byte(bitstream);
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for(int i=1;i<len&&ret!=0xFFFFFFFF;i++){
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ret<<=8;
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ret|=get_byte(bitstream);
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}
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return ret;
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}
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void FPGA_write(FPGA_t* FPGA,bitstream_t* bitstream){
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int n=FPGA->CRAM_colsize*FPGA->CRAM_rowsize/8;
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uint8_t* temp=(uint8_t*)malloc(n);
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for(int i=0;i<n;i++)
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temp[i]=get_byte(bitstream);
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FPGA->CRAM[FPGA->bank]=temp;
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}
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void FPGA_EBR_write(FPGA_t* FPGA,bitstream_t* bitstream){
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int n=FPGA->BRAM_colsize*FPGA->BRAM_rowsize/8;
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uint8_t* temp=(uint8_t*)malloc(FPGA->write_pointer+n);
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if(FPGA->write_pointer!=0){
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uint8_t* old_data=FPGA->BRAM[FPGA->bank];
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memcpy(temp,old_data,FPGA->write_pointer);
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free(old_data);
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}
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for(int i=0;i<n;i++)temp[FPGA->write_pointer++]=get_byte(bitstream);
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FPGA->BRAM[FPGA->bank]=temp;
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}
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int parse(bitstream_t* bitstream, FPGA_t* FPGA) {
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uint32_t preamble=0;
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while(1){
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preamble<<=8;
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preamble|=get_byte(bitstream);
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if(preamble==0x7EAA997E){
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debugf("Got preamble\n");
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break;
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}
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if(preamble==0xFFFFFFFF){
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fprintf(stderr,"Error: could not find preamble...\n");
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return -1;
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}
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}
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nibble_t command;
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uint32_t payload;
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uint16_t crc;
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while(1){
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crc=bitstream->crc;
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command.full=get_byte(bitstream);
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if(command.full==0xFF){
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payload=get_byte(bitstream);
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if(payload!=0x00)goto err;
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char*comment=(char*)&bitstream->payload[bitstream->pointer];
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debugf("Got comment section start\n");
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while(1){
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payload<<=8;
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payload|=get_byte(bitstream);
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if((payload&0xFFFF)==0x00FF)break;
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if(payload==0xFFFFFFFF){
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fprintf(stderr,"Error: could not find comment section end\n");
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return -1;
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}
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}
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debugf("\n%s\n\n",comment);
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debugf("Got comment section end\n");
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continue;
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}
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payload=get_payload(bitstream,command.lo);
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switch(command.hi){
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case 0x0:
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if(command.lo!=0x01)goto err;
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switch(payload){
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case 0x01:
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debugf("Write to CRAM!!!\n");
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FPGA_write(FPGA,bitstream);
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get_payload(bitstream,2);
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break;
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case 0x03:
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debugf("Write to BRAM!!!\n");
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FPGA_EBR_write(FPGA,bitstream);
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get_payload(bitstream,2);
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break;
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case 0x05:
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debugf("Resetting CRC\n");
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bitstream->crc=0;
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break;
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case 0x06:
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debugf("Wake up\n");
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return 0;
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default:
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goto err;
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}
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break;
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case 0x1:
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if(command.lo!=0x01)goto err;
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if(payload>3){
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fprintf(stderr,"Error: bank %u does not exist...\n",payload);
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}
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debugf("Set bank to %u\n",payload);
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FPGA->bank=payload;
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break;
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case 0x2:
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if(command.lo!=0x02)goto err;
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debugf("CRC check: %04X %04X\n",payload,crc);
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break;
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case 0x5:
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if(command.lo!=0x01)goto err;
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if(payload>2){
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fprintf(stderr,"Error: unknown frequency setting...\n");
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return -1;
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}
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debugf("Boot frequency set to %s\n",freq_settings[payload]);
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FPGA->freq=payload;
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break;
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case 0x6:
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if(command.lo!=0x02)goto err;
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payload++;
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debugf("Row size: %i\n",payload);
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if(FPGA->CRAM_rowsize)FPGA->BRAM_rowsize=payload;
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else FPGA->CRAM_rowsize=payload;
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break;
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case 0x7:
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if(command.lo!=0x02)goto err;
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debugf("Column size: %i\n",payload);
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if(FPGA->CRAM_colsize)FPGA->BRAM_colsize=payload;
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else FPGA->CRAM_colsize=payload;
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break;
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case 0x8:
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if(command.lo!=0x02)goto err;
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if(payload==0x0000){
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debugf("Reset write pointer\n");
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FPGA->write_pointer=0;
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}
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else if(payload==0x0080){
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debugf("Don't reset write pointer\n");
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}
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else goto err;
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break;
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case 0x9:
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if(command.lo!=0x02)goto err;
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if(payload&0xFFDF){
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fprintf(stderr,"Error: Unknown warmboot setting... %04X\n",payload);
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return -1;
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}
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debugf("%s warmboot\n",boot_settings[payload?1:0]);
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FPGA->boot_mode=payload;
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break;
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default:
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goto err;
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}
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}
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err:
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fprintf(stderr,"Error: unkown command... %08X\n",bitstream->pointer);
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return -1;
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}
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uint8_t get_CRAM_bit_from_sector(FPGA_t* FPGA,int bank,int x,int y){
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if(x<0||x>=FPGA->CRAM_rowsize)return 0xFF;
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if(y<0||y>=FPGA->CRAM_colsize)return 0xFF;
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if(bank<0||bank>=4)return 0xFF;
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int bit=y*FPGA->CRAM_rowsize+x;
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int pointer=bit>>3;
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int shifts=7-(bit&7);
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return (FPGA->CRAM[bank][pointer]>>shifts)&1;
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}
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int tiles[2][20]={
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{18,54,54,42,54,54,54},
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{18,2,54,54,54,54,54,54,54,42,54,54,54,54,54,54,54,54}
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};
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int permx[2][18]={
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{23,25,26,27,16,17,18,19,20,14,32,33,34,35,36,37,4,5},
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{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17}};
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int permy[4][16]={
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{0,1,3,2,4,5,7,6,8,9,11,10,12,13,15,14},
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{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15},
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};
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int tile_row_size[2]={7,17};
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int tile_col_size[2]={9,17};
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void print_tile(FPGA_t* FPGA,int x,int y){
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int type=FPGA->CRAM_rowsize==872;
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int dirx=0;
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int diry=0;
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int tx=x;
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int ty=y;
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|
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int corner_flags=0;
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if(x==0)corner_flags|=1;
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if(y==0)corner_flags|=2;
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if(x==tile_row_size[type]*2-1)corner_flags|=4;
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if(y==tile_col_size[type]*2-1)corner_flags|=8;
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if(corner_flags&(corner_flags-1))
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return;
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if(x>=tile_row_size[type]){
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dirx=1;
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tx=tile_row_size[type]*2-1-x;
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}
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if(y>=tile_col_size[type]){
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diry=1;
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ty=tile_col_size[type]*2-1-y;
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}
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int sector=(diry|dirx<<1);
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int offx=0;for(int i=0;i<tx;i++)offx+=tiles[type][i];
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if(corner_flags){
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printf(".io_tile %i %i\n",x,y);
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for(int cy=0;cy<16;cy++){
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for(int cx=0;cx<18;cx++){
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int val;
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if(corner_flags&5){
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if(diry){
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val=get_CRAM_bit_from_sector(FPGA,sector,offx+tiles[type][tx]-1-permx[1][cx],ty*16+15-permy[1][cy]);
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}else{
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val=get_CRAM_bit_from_sector(FPGA,sector,offx+tiles[type][tx]-1-permx[1][cx],ty*16+permy[1][cy]);
|
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}
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}else{
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if(dirx){
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val=get_CRAM_bit_from_sector(FPGA,sector,offx+tiles[type][tx]-1-permx[0][cx],ty*16+15-permy[0][cy]);
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}else{
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val=get_CRAM_bit_from_sector(FPGA,sector,offx+permx[0][cx],ty*16+15-permy[0][cy]);
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}
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}
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printf("%i",val);
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}
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printf("\n");
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}
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}
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else{
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if(tiles[type][tx]==20)printf(".io_tile %i %i\n",x,y);
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if(tiles[type][tx]==42)printf(".ram_tile %i %i\n",x,y);
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if(tiles[type][tx]==54)printf(".logic_tile %i %i\n",x,y);
|
||||
for(int cy=0;cy<16;cy++){
|
||||
for(int cx=0;cx<tiles[type][tx];cx++){
|
||||
printf("%i",get_CRAM_bit_from_sector(FPGA,sector,(dirx?(offx+tiles[type][tx]-1-cx):(offx+cx)),(diry?(ty*16+(15-cy)):(ty*16+cy))));
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(int argc,char**argv) {
|
||||
if(argc>=2&&!strcmp(argv[1], "-v")) {
|
||||
enable_debug=1;
|
||||
argc--;
|
||||
argv++;
|
||||
}
|
||||
if(argc!=2) {
|
||||
fprintf(stderr,"iceunpack [-v] input\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
FILE*r_file=fopen(argv[1],"rb");
|
||||
if(r_file==NULL) {
|
||||
fprintf(stderr,"could not open %s\n",argv[1]);
|
||||
return 1;
|
||||
}
|
||||
fseek(r_file,0,SEEK_END);
|
||||
size_t r_size=ftell(r_file);
|
||||
fseek(r_file,0,SEEK_SET);
|
||||
|
||||
bitstream_t* bitstream=(bitstream_t*)malloc(sizeof(bitstream_t)+r_size);
|
||||
bitstream->len=r_size;
|
||||
bitstream->pointer=0;
|
||||
fread(bitstream->payload,1,r_size,r_file);
|
||||
fclose(r_file);
|
||||
|
||||
FPGA_t FPGA;
|
||||
memset(&FPGA,0,sizeof(FPGA));
|
||||
|
||||
parse(bitstream,&FPGA);
|
||||
free(bitstream);
|
||||
|
||||
printf(".device 1k\n");
|
||||
for(int y=0;y<18;y++)for(int x=0;x<14;x++)print_tile(&FPGA,x,y);
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue