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< title > Project IceStorm – RAM Tile Documentation< / title >
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< / head > < body >
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< h1 > Project IceStorm – RAM Tile Documentation< / h1 >
< p >
< i > < a href = "." > Project IceStorm< / a > aims at documenting the bitstream format of Lattice iCE40
FPGAs and providing simple tools for analyzing and creating bitstream files.
This is work in progress.< / i >
< / p >
< h2 > Span-4 and Span-12 Wires< / h2 >
< p >
Regarding the Span-4 and Span-12 Wires a RAM tile behaves exactly like a LOGIC tile. So for simple
applications that do not need the block ram resources, the RAM tiles can be handled like a LOGIC
tiles without logic cells in them.
< / p >
< h2 > Block RAM Resources< / h2 >
< p >
A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with
LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram
inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates
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are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a < span style = "font-family:monospace" > SB_RAM40_4K< / span > cell. The
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cell ports are spread out over the two tiles as follows:
< / p >
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< table class = "ctab" >
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< tr > < th > SB_RAM40_4K< / th > < th > RAMB Tile< / th > < th > RAMT Tile< / th > < / tr >
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< tr > < td > < span style = "font-family:monospace" > RDATA[15:0]< / span > < / td > < td > < span style = "font-family:monospace" > RDATA[7:0]< / span > < / td > < td > < span style = "font-family:monospace" > RDATA[15:8]< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > RADDR[10:0]< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < td > < span style = "font-family:monospace" > RADDR[10:0]< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > WADDR[10:0]< / span > < / td > < td > < span style = "font-family:monospace" > WADDR[10:0]< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > MASK[15:0]< / span > < / td > < td > < span style = "font-family:monospace" > MASK[7:0]< / span > < / td > < td > < span style = "font-family:monospace" > MASK[15:8]< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > WDATA[15:0]< / span > < / td > < td > < span style = "font-family:monospace" > WDATA[7:0]< / span > < / td > < td > < span style = "font-family:monospace" > WDATA[15:8]< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > RCLKE< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < td > < span style = "font-family:monospace" > RCLKE< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > RCLK< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < td > < span style = "font-family:monospace" > RCLK< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > RE< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < td > < span style = "font-family:monospace" > RE< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > WCLKE< / span > < / td > < td > < span style = "font-family:monospace" > WCLKE< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > WCLK< / span > < / td > < td > < span style = "font-family:monospace" > WCLK< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > WE< / span > < / td > < td > < span style = "font-family:monospace" > WE< / span > < / td > < td > < span style = "font-family:monospace" > -< / span > < / td > < / tr >
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< / table >
< p >
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The configuration bit < span style = "font-family:monospace" > RamConfig PowerUp< / span > in the RAMB tile enables the memory. This bit
is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that < span style = "font-family:monospace" > icebox_explain.py< / span >
will ignore all RAMB tiles that only have the < span style = "font-family:monospace" > RamConfig PowerUp< / span > bit set.
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< / p >
< p >
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In 8k chips the < span style = "font-family:monospace" > RamConfig PowerUp< / span > bit is active-high. So an unused RAM block has all bits cleared
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in the 8k config bitstream.
< / p >
< p >
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The < span style = "font-family:monospace" > RamConfig CBIT_*< / span > bits in the RAMT tile configure the read/write width of the
memory. Those bits map to the < span style = "font-family:monospace" > SB_RAM40_4K< / span > cell parameters as follows:
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< / p >
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< table class = "ctab" >
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< tr > < th > SB_RAM40_4K< / th > < th > RAMT Config Bit< / th > < / tr >
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< tr > < td > < span style = "font-family:monospace" > WRITE_MODE[0]< / span > < / td > < td > < span style = "font-family:monospace" > RamConfig CBIT_0< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > WRITE_MODE[1]< / span > < / td > < td > < span style = "font-family:monospace" > RamConfig CBIT_1< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > READ_MODE[0]< / span > < / td > < td > < span style = "font-family:monospace" > RamConfig CBIT_2< / span > < / td > < / tr >
< tr > < td > < span style = "font-family:monospace" > READ_MODE[1]< / span > < / td > < td > < span style = "font-family:monospace" > RamConfig CBIT_3< / span > < / td > < / tr >
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< / table >
< p >
The read/write mode selects the width of the read/write port:
< / p >
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< table class = "ctab" >
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< tr > < th > MODE< / th > < th > DATA Width< / th > < th > Used WDATA/RDATA Bits< / th > < / tr >
< tr > < td > 0< / td > < td > 16< / td > < td > 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0< / td > < / tr >
< tr > < td > 1< / td > < td > 8< / td > < td > 14, 12, 10, 8, 6, 4, 2, 0< / td > < / tr >
< tr > < td > 2< / td > < td > 4< / td > < td > 13, 9, 5, 1< / td > < / tr >
< tr > < td > 3< / td > < td > 2< / td > < td > 11, 3< / td > < / tr >
< / table >
< p >
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The < span style = "font-family:monospace" > NegClk< / span > bit in the RAMB tile negates the polarity of the < span style = "font-family:monospace" > WCLK< / span > port,
and the < span style = "font-family:monospace" > NegClk< / span > bit in the RAMT tile negates the polarity of the < span style = "font-family:monospace" > RCLK< / span > port.
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< / p >
< p >
A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing
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with the < span style = "font-family:monospace" > RDATA< / span > outputs. Each RAMB tile exports its < span style = "font-family:monospace" > RDATA[7:0]< / span > outputs and each RAMT tile
exports its < span style = "font-family:monospace" > RDATA[15:8]< / span > outputs via this mechanism.
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< / p >
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