mirror of https://github.com/YosysHQ/icestorm.git
524 lines
22 KiB
Python
524 lines
22 KiB
Python
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#!/usr/bin/python
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#
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# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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from __future__ import division
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from __future__ import print_function
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import icebox
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import getopt, sys, os, re
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chipname = "iCE40 HX1K"
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outdir = None
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tx, ty = 0, 0
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def usage():
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print("Usage: %s [options]" % sys.argv[0])
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print(" -x tile_x_coordinate")
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print(" -y tile_y_coordinate")
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print(" -d outdir")
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sys.exit(0)
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try:
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opts, args = getopt.getopt(sys.argv[1:], "x:y:d:")
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except:
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usage()
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for o, a in opts:
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if o == "-x":
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tx = int(a)
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elif o == "-y":
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ty = int(a)
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elif o == "-d":
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outdir = a
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else:
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usage()
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ic = icebox.iceconfig()
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ic.setup_empty_1k()
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mktiles = set()
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for x in range(1, 6) + range(8, 13):
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mktiles.add((x, 0))
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mktiles.add((x, 17))
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for x in range(0, 6) + range(8, 14):
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mktiles.add((x, 1))
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mktiles.add((x, 16))
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for x in range(0, 5) + range(9, 14):
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mktiles.add((x, 2))
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mktiles.add((x, 15))
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for x in range(6, 8):
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for y in range(8, 10):
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mktiles.add((x, y))
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expand_count=[0]
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def print_expand_div(title):
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print('<a id="exph%d" href="#" onclick="document.getElementById(\'exph%d\').style.display=\'none\'; document.getElementById(\'exp%d\').style.display=\'block\'; return false">[+] Show %s</a><div id="exp%d" style="display:none">' % (expand_count[0], expand_count[0], expand_count[0], title, expand_count[0]))
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expand_count[0] += 1
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def print_expand_end():
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print('</div>')
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def print_expand_all():
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print('<a id="exph%d" href="#" onclick="for (i = 0; i < 100; i++) { document.getElementById(\'exph\'+i).style.display=\'none\'; document.getElementById(\'exp\'+i).style.display=\'block\'; }; return false">[+] Expand All</a><span id="exp%d" style="display:none"></span>' % (expand_count[0], expand_count[0]))
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expand_count[0] += 1
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def print_index():
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print("<title>Project IceStorm – %s Overview</title>" % chipname)
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print("<h1>Project IceStorm – %s Overview</h1>" % chipname)
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print("""<i><a href="http://www.clifford.at/icestorm/">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40 FPGAs
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and providing simple tools for analyzing and creating bitstream files. This is work in progress.</i>""")
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print("""<p>This documentation is auto-generated by <tt>icebox_html.py</tt> from IceBox.<br/>
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A machine-readable form of the database can be downloaded <a href="chipdb.txt">here</a>.</p>""")
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print("""<p>The iCE40 FPGA fabric is organized into tiles. The configuration bits
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themself have the same meaning in all tiles of the same type. But the way the tiles
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are connected to each other depends on the types of neighbouring cells. Furthermore,
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some wire names are different for (e.g.) a IO tile on the left border and an IO tile on
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the top border.</p>""")
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print("""<p>Click on a highlighted tile below to view the bitstream details for the
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tile. The highlighted tiles cover all combinations of neighbouring cells that can be found
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in iCE40 FPGAs.</p>""")
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print('<p><table border="1">')
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for y in range(ic.max_y, -1, -1):
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print("<tr>")
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for x in range(ic.max_x + 1):
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print('<td style="width:50px; height:50px;" align="center" valign="center"', end="")
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if ic.tile_pos(x, y) == None:
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print('> </td>')
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elif (x, y) in mktiles:
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if ic.tile_type(x, y) == "IO": color = "#aee"
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if ic.tile_type(x, y) == "LOGIC": color = "#eae"
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if ic.tile_type(x, y) == "RAM": color = "#eea"
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print('bgcolor="%s"><small><a style="color:#000; text-decoration:none" href="tile_%d_%d.html"><b>%s<br/>(%d %d)</b></a></small></td>' % (color, x, y, ic.tile_type(x, y), x, y))
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else:
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if ic.tile_type(x, y) == "IO": color = "#8aa"
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if ic.tile_type(x, y) == "LOGIC": color = "#a8a"
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if ic.tile_type(x, y) == "RAM": color = "#aa8"
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print('bgcolor="%s"><small>%s<br/>(%d %d)</small></td>' % (color, ic.tile_type(x, y), x, y))
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print("</tr>")
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print("</table></p>")
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def print_tile(tx, ty):
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tile = ic.tile(tx, ty)
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tile_type = ic.tile_type(tx, ty)
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print("<title>Project IceStorm – %s %s Tile (%d %d)</title>" % (chipname, tile_type, tx, ty))
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print("<h1>Project IceStorm – %s %s Tile (%d %d)</h1>" % (chipname, tile_type, tx, ty))
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print("""<i><a href="http://www.clifford.at/icestorm/">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40 FPGAs
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and providing simple tools for analyzing and creating bitstream files. This is work in progress.</i>""")
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print("""<p>This page describes the %s Tile (%d %d), what nets and
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configuration bits it has and how it is connected to its neighbourhood.</p>""" % (tile_type, tx, ty))
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visible_tiles = set()
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print('<p><table border="1">')
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for y in range(ty+2, ty-3, -1):
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print("<tr>")
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for x in range(tx-2, tx+3):
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print('<td style="width:100px; height:70px;" align="center" valign="center"', end="")
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if ic.tile_pos(x, y) == None:
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print('> </td>')
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else:
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if (x, y) in mktiles:
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if ic.tile_type(x, y) == "IO": color = "#aee"
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if ic.tile_type(x, y) == "LOGIC": color = "#eae"
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if ic.tile_type(x, y) == "RAM": color = "#eea"
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print('bgcolor="%s"><a style="color:#000; text-decoration:none" href="tile_%d_%d.html"><b>%s Tile<br/>(%d %d)</b></a></td>' % (color, x, y, ic.tile_type(x, y), x, y))
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else:
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if ic.tile_type(x, y) == "IO": color = "#8aa"
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if ic.tile_type(x, y) == "LOGIC": color = "#a8a"
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if ic.tile_type(x, y) == "RAM": color = "#aa8"
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print('bgcolor="%s">%s Tile<br/>(%d %d)</td>' % (color, ic.tile_type(x, y), x, y))
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visible_tiles.add((x, y))
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print("</tr>")
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print("</table></p>")
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# print_expand_all()
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print("<h2>Configuration Bitmap</h2>")
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print("<p>A %s Tile has %d config bits in %d groups of %d bits each:<br/>" % (tile_type, len(tile)*len(tile[0]), len(tile), len(tile[0])))
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print(("<tt>%s</tt></p>" % (", ".join(['%sB%d[%d:0]' % (" " if i < 10 else "", i, len(tile[i])-1) for i in range(len(tile))]))).replace(" B8", "<br/> B8"))
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bitmap_cells = list()
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for line_nr in range(len(tile)):
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line = list()
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bitmap_cells.append(line)
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for bit_nr in range(len(tile[line_nr])):
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line.append({"bgcolor": "#aaa", "label": "?"})
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for entry in ic.tile_db(tx, ty):
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if not ic.tile_has_entry(tx, ty, entry):
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continue
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for bit in [bit.replace("!", "") for bit in entry[0]]:
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match = re.match(r"B(\d+)\[(\d+)\]$", bit)
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idx1 = int(match.group(1))
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idx2 = int(match.group(2))
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if entry[1] == "routing":
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bitmap_cells[idx1][idx2]["bgcolor"] = "#faa"
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bitmap_cells[idx1][idx2]["label"] = "R"
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bitmap_cells[idx1][idx2]["is_routing"] = True
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elif entry[1] == "buffer":
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bitmap_cells[idx1][idx2]["bgcolor"] = "#afa"
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bitmap_cells[idx1][idx2]["label"] = "B"
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bitmap_cells[idx1][idx2]["is_routing"] = True
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else:
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bitmap_cells[idx1][idx2]["bgcolor"] = "#aaf"
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if entry[1] == "ColBufCtrl":
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bitmap_cells[idx1][idx2]["label"] = "O"
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elif entry[1].startswith("LC_"):
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bitmap_cells[idx1][idx2]["label"] = "L"
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elif entry[1].startswith("NegClk"):
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bitmap_cells[idx1][idx2]["label"] = "N"
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elif entry[1].startswith("CarryInSet"):
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bitmap_cells[idx1][idx2]["label"] = "C"
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elif entry[1].startswith("IOB_"):
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bitmap_cells[idx1][idx2]["label"] = "I"
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elif entry[1].startswith("IoCtrl"):
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bitmap_cells[idx1][idx2]["label"] = "I"
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elif entry[1].startswith("Cascade"):
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bitmap_cells[idx1][idx2]["label"] = "A"
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elif entry[1].startswith("RamConfig"):
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bitmap_cells[idx1][idx2]["label"] = "R"
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else:
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assert False
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bitmap_cells[idx1][idx2]["label"] = '<a style="color:#666; text-decoration:none" href="#B.%d.%d">%s</a>' % (idx1, idx2, bitmap_cells[idx1][idx2]["label"])
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print('<table style="font-size:small">')
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print("<tr><td></td>")
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for cell_nr in range(len(line)):
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print('<td align="center" width="15">%d</td>' % cell_nr)
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print("<td></td></tr>")
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for line_nr, line in enumerate(bitmap_cells):
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print("<tr>")
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print('<td>B%d</td>' % line_nr)
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for cell in line:
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print('<td align="center" bgcolor="%s" style="color:#666;">%s</td>' % (cell["bgcolor"], cell["label"]))
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print('<td>B%d</td>' % line_nr)
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print("</tr>")
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print("<tr><td></td>")
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for cell_nr in range(len(line)):
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print('<td align="center">%d</td>' % cell_nr)
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print("<td></td></tr>")
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print("</table>")
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print("<h2>Nets and Connectivity</h2>")
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print("""<p>This section lists all nets in the tile and how this
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nets are connected with nets from cells in its neighbourhood.</p>""")
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grouped_segs = ic.group_segments(set([(tx, ty)]))
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groups_indexed = dict()
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this_tile_nets = dict()
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for segs in sorted(grouped_segs):
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this_segs = list()
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neighbour_segs = dict()
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for s in segs:
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if s[0] == tx and s[1] == ty:
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this_segs.append(s[2])
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match = re.match(r"(.*?_)(\d+)(.*)", s[2])
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if match:
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this_tile_nets.setdefault(match.group(1) + "*" + match.group(3), set()).add(int(match.group(2)))
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else:
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this_tile_nets.setdefault(s[2], set()).add(-1)
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if (s[0], s[1]) in visible_tiles:
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neighbour_segs.setdefault((s[0], s[1]), list()).append(s[2])
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if this_segs:
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this_name = ", ".join(sorted(this_segs))
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assert this_name not in groups_indexed
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groups_indexed[this_name] = neighbour_segs
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print("<h3>List of nets in %s Tile (%d %d)</h3>" % (tile_type, tx, ty))
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def net2cat(netname):
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cat = (99, "Unsorted")
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if netname.startswith("glb_netwk_"): cat = (10, "Global Networks")
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if netname.startswith("glb2local_"): cat = (10, "Global Networks")
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if netname.startswith("wire_gbuf"): cat = (10, "Global Networks")
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if netname.startswith("local_"): cat = (20, "Local Tracks")
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if netname.startswith("carry_in"): cat = (25, "Logic Block")
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if netname.startswith("io_"): cat = (25, "IO Block")
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if netname.startswith("lutff_"): cat = (25, "Logic Block")
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if netname.startswith("lutff_0"): cat = (30, "Logic Unit 0")
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if netname.startswith("lutff_1"): cat = (30, "Logic Unit 1")
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if netname.startswith("lutff_2"): cat = (30, "Logic Unit 2")
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if netname.startswith("lutff_3"): cat = (30, "Logic Unit 3")
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if netname.startswith("lutff_4"): cat = (30, "Logic Unit 4")
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if netname.startswith("lutff_5"): cat = (30, "Logic Unit 5")
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if netname.startswith("lutff_6"): cat = (30, "Logic Unit 6")
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if netname.startswith("lutff_7"): cat = (30, "Logic Unit 7")
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if netname.startswith("neigh_op_"): cat = (40, "Neighbourhood")
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if netname.startswith("logic_op_"): cat = (40, "Neighbourhood")
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if netname.startswith("sp4_v_"): cat = (50, "Span-4 Vertical")
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if netname.startswith("span4_vert_"): cat = (50, "Span-4 Vertical")
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if netname.startswith("sp4_r_v_"): cat = (55, "Span-4 Right Vertical")
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if netname.startswith("sp4_h_"): cat = (60, "Span-4 Horizontal")
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if netname.startswith("span4_horz_"): cat = (60, "Span-4 Horizontal")
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if netname.startswith("sp12_v_"): cat = (70, "Span-12 Vertical")
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if netname.startswith("span12_vert_"): cat = (70, "Span-12 Vertical")
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if netname.startswith("sp12_h_"): cat = (80, "Span-12 Horizontal")
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if netname.startswith("span12_horz_"): cat = (80, "Span-12 Horizontal")
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return cat
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nets_in_cats = dict()
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for this_name in sorted(this_tile_nets):
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nets_in_cats.setdefault(net2cat(this_name), list()).append(this_name)
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for cat in sorted(nets_in_cats):
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print('<h4>%s</h4>' % cat[1])
|
||
|
|
print('<p><ul style="margin:0">')
|
||
|
|
for this_name in sorted(nets_in_cats[cat]):
|
||
|
|
indices = [i for i in this_tile_nets[this_name] if i >= 0]
|
||
|
|
if -1 in this_tile_nets[this_name]:
|
||
|
|
print("<li><tt>%s</tt></li>" % this_name)
|
||
|
|
if len(indices) == 1:
|
||
|
|
print("<li><tt>%s</tt></li>" % this_name.replace("*", "%d" % indices[0]))
|
||
|
|
elif len(indices) > 0:
|
||
|
|
print("<li><tt>%s</tt></li>" % this_name.replace("*", "{" + ",".join(["%d" % i for i in sorted(indices)]) + "}"))
|
||
|
|
print("</ul></p>")
|
||
|
|
|
||
|
|
print("<h3>Nets and their permanent connections to nets in neighbour tiles</h3>")
|
||
|
|
|
||
|
|
# print_expand_div("connection details")
|
||
|
|
|
||
|
|
all_cats = set()
|
||
|
|
for this_name in sorted(groups_indexed):
|
||
|
|
all_cats.add(net2cat(this_name))
|
||
|
|
|
||
|
|
for cat in sorted(all_cats):
|
||
|
|
print('<h4>%s</h4>' % cat[1])
|
||
|
|
print('<p><div style="-webkit-column-count: 3; -moz-column-count: 3; column-count: 3;"><ul style="margin:0">')
|
||
|
|
for this_name in sorted(groups_indexed):
|
||
|
|
if net2cat(this_name) == cat:
|
||
|
|
neighbour_segs = groups_indexed[this_name]
|
||
|
|
print("<li><tt><b>%s</b></tt>" % this_name)
|
||
|
|
if neighbour_segs:
|
||
|
|
print("<ul>")
|
||
|
|
for nidx in sorted(neighbour_segs):
|
||
|
|
if nidx == (tx, ty):
|
||
|
|
print("<li><tt><b>(%d %d)</b> %s</tt></li>" % (nidx[0], nidx[1], ", ".join(sorted(neighbour_segs[nidx]))))
|
||
|
|
else:
|
||
|
|
print("<li><tt>(%d %d) %s</tt></li>" % (nidx[0], nidx[1], ", ".join(sorted(neighbour_segs[nidx]))))
|
||
|
|
print("</ul>")
|
||
|
|
print("</li>")
|
||
|
|
print("</ul></div></p>")
|
||
|
|
|
||
|
|
# print_expand_end()
|
||
|
|
|
||
|
|
print("<h2>Routing Configuration</h2>")
|
||
|
|
|
||
|
|
print("""<p>This section lists the routing configuration bits in the tile.
|
||
|
|
The entries titled "routing" configure transfer gates, the entries titled
|
||
|
|
"buffer" configure tri-state drivers.</p>""")
|
||
|
|
|
||
|
|
grpgrp = dict()
|
||
|
|
config_groups = dict()
|
||
|
|
other_config_groups = dict()
|
||
|
|
|
||
|
|
for entry in ic.tile_db(tx, ty):
|
||
|
|
if not ic.tile_has_entry(tx, ty, entry):
|
||
|
|
continue
|
||
|
|
if entry[1] in ("routing", "buffer"):
|
||
|
|
cfggrp = entry[1] + " " + entry[3] + "," + ",".join(sorted([bit.replace("!", "") for bit in entry[0]]))
|
||
|
|
config_groups.setdefault(cfggrp, list()).append(entry)
|
||
|
|
grpgrp.setdefault(net2cat(entry[3]), set()).add(cfggrp)
|
||
|
|
else:
|
||
|
|
grp = other_config_groups.setdefault(" ".join(entry[1:]), set())
|
||
|
|
for bit in entry[0]: grp.add(bit)
|
||
|
|
|
||
|
|
for cat in sorted(grpgrp):
|
||
|
|
print('<h4>%s</h4>' % cat[1])
|
||
|
|
|
||
|
|
bits_in_cat = set()
|
||
|
|
|
||
|
|
for cfggrp in sorted(grpgrp[cat]):
|
||
|
|
grp = config_groups[cfggrp]
|
||
|
|
for bit in cfggrp.split(",")[1:]:
|
||
|
|
match = re.match(r"B(\d+)\[(\d+)\]", bit)
|
||
|
|
bits_in_cat.add((int(match.group(1)), int(match.group(2))))
|
||
|
|
|
||
|
|
print('<table style="font-size:x-small">')
|
||
|
|
print("<tr><td></td>")
|
||
|
|
for cell_nr in range(len(bitmap_cells[0])):
|
||
|
|
print('<td align="center" width="15">%d</td>' % cell_nr)
|
||
|
|
print("<td></td></tr>")
|
||
|
|
for line_nr, line in enumerate(bitmap_cells):
|
||
|
|
print("<tr>")
|
||
|
|
print('<td>B%d</td>' % line_nr)
|
||
|
|
for cell_nr, cell in enumerate(line):
|
||
|
|
color = cell["bgcolor"]
|
||
|
|
if (line_nr, cell_nr) not in bits_in_cat: color="#aaa"
|
||
|
|
print('<td align="center" bgcolor="%s" style="color:#666;">%s</td>' % (color, cell["label"]))
|
||
|
|
print('<td>B%d</td>' % line_nr)
|
||
|
|
print("</tr>")
|
||
|
|
print("<tr><td></td>")
|
||
|
|
for cell_nr in range(len(line)):
|
||
|
|
print('<td align="center">%d</td>' % cell_nr)
|
||
|
|
print("<td></td></tr>")
|
||
|
|
print("</table>")
|
||
|
|
|
||
|
|
# print_expand_div("details")
|
||
|
|
|
||
|
|
src_nets = set()
|
||
|
|
dst_nets = set()
|
||
|
|
links = dict()
|
||
|
|
|
||
|
|
for cfggrp in sorted(grpgrp[cat]):
|
||
|
|
grp = config_groups[cfggrp]
|
||
|
|
for entry in grp:
|
||
|
|
src_nets.add(entry[2])
|
||
|
|
dst_nets.add(entry[3])
|
||
|
|
if entry[1] == "buffer":
|
||
|
|
assert (entry[2], entry[3]) not in links
|
||
|
|
links[(entry[2], entry[3])] = '<td align="center" bgcolor="#afa" style="color:#666;">B</td>'
|
||
|
|
else:
|
||
|
|
assert (entry[2], entry[3]) not in links
|
||
|
|
links[(entry[2], entry[3])] = '<td align="center" bgcolor="#faa" style="color:#666;">R</td>'
|
||
|
|
|
||
|
|
print('<h5>Connectivity Matrix</h5>')
|
||
|
|
print('<table style="font-size:x-small">')
|
||
|
|
dst_net_prefix = ""
|
||
|
|
dst_net_list = sorted(dst_nets, icebox.cmp_netnames)
|
||
|
|
if len(dst_net_list) > 1:
|
||
|
|
while len(set([n[0] for n in dst_net_list])) == 1:
|
||
|
|
dst_net_prefix += dst_net_list[0][0]
|
||
|
|
for i in range(len(dst_net_list)):
|
||
|
|
dst_net_list[i] = dst_net_list[i][1:]
|
||
|
|
while dst_net_prefix != "" and dst_net_prefix[-1] != "_":
|
||
|
|
for i in range(len(dst_net_list)):
|
||
|
|
dst_net_list[i] = dst_net_prefix[-1] + dst_net_list[i]
|
||
|
|
dst_net_prefix = dst_net_prefix[0:-1]
|
||
|
|
print('<tr><td></td><td colspan="%d" align="center">%s</td></tr>' % (len(dst_net_list), dst_net_prefix))
|
||
|
|
print('<tr><td></td>')
|
||
|
|
for dn in dst_net_list:
|
||
|
|
print('<td>%s</td>' % dn)
|
||
|
|
print("</tr>")
|
||
|
|
for sn in sorted(src_nets, icebox.cmp_netnames):
|
||
|
|
print("<tr>")
|
||
|
|
print('<td>%s</td>' % sn)
|
||
|
|
for dn in sorted(dst_nets, icebox.cmp_netnames):
|
||
|
|
if (sn, dn) in links:
|
||
|
|
print(links[(sn, dn)])
|
||
|
|
else:
|
||
|
|
print('<td align="center" bgcolor="#aaa" style="color:#666;"> </td>')
|
||
|
|
print("</tr>")
|
||
|
|
print("</table>")
|
||
|
|
|
||
|
|
print('<h5>Configuration Stamps</h5>')
|
||
|
|
for cfggrp in sorted(grpgrp[cat]):
|
||
|
|
grp = config_groups[cfggrp]
|
||
|
|
bits = cfggrp.split(",")[1:]
|
||
|
|
print('<p><table style="font-size:small" border><tr>')
|
||
|
|
for bit in bits:
|
||
|
|
print('<th style="width:5em"><a name="%s">%s</a></th>' % (re.sub(r"B(\d+)\[(\d+)\]", r"B.\1.\2", bit), bit))
|
||
|
|
group_lines = list()
|
||
|
|
is_buffer = True
|
||
|
|
for entry in grp:
|
||
|
|
line = '<tr>'
|
||
|
|
for bit in bits:
|
||
|
|
if bit in entry[0]:
|
||
|
|
line += '<td align="center">1</td>'
|
||
|
|
else:
|
||
|
|
line += '<td align="center">0</td>'
|
||
|
|
is_buffer = entry[1] == "buffer"
|
||
|
|
line += '<td align="center">%s</td><td><tt>%s</tt></td><td><tt>%s</tt></td></tr>' % (entry[1], entry[2], entry[3])
|
||
|
|
group_lines.append(line)
|
||
|
|
if is_buffer:
|
||
|
|
print('<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>')
|
||
|
|
else:
|
||
|
|
print('<th style="width:5em">Function</th><th style="width:15em">Net</th><th style="width:15em">Net</th></tr>')
|
||
|
|
for line in sorted(group_lines):
|
||
|
|
print(line)
|
||
|
|
print('</table></p>')
|
||
|
|
|
||
|
|
# print_expand_end()
|
||
|
|
|
||
|
|
print("<h2>Non-routing Configuration</h2>")
|
||
|
|
|
||
|
|
print("<p>This section lists the non-routing configuration bits in the tile.</p>")
|
||
|
|
|
||
|
|
print('<table style="font-size:x-small">')
|
||
|
|
print("<tr><td></td>")
|
||
|
|
for cell_nr in range(len(bitmap_cells[0])):
|
||
|
|
print('<td align="center" width="15">%d</td>' % cell_nr)
|
||
|
|
print("<td></td></tr>")
|
||
|
|
for line_nr, line in enumerate(bitmap_cells):
|
||
|
|
print("<tr>")
|
||
|
|
print('<td>B%d</td>' % line_nr)
|
||
|
|
for cell_nr, cell in enumerate(line):
|
||
|
|
color = cell["bgcolor"]
|
||
|
|
if "is_routing" in cell: color="#aaa"
|
||
|
|
print('<td align="center" bgcolor="%s" style="color:#666;">%s</td>' % (color, cell["label"]))
|
||
|
|
print('<td>B%d</td>' % line_nr)
|
||
|
|
print("</tr>")
|
||
|
|
print("<tr><td></td>")
|
||
|
|
for cell_nr in range(len(line)):
|
||
|
|
print('<td align="center">%d</td>' % cell_nr)
|
||
|
|
print("<td></td></tr>")
|
||
|
|
print("</table>")
|
||
|
|
|
||
|
|
print('<p><table style="font-size:small" border><tr><th>Function</th><th>Bits</th></tr>')
|
||
|
|
for cfggrp in sorted(other_config_groups):
|
||
|
|
bits = " ".join(['<a name="%s">%s</a>' % (re.sub(r"B(\d+)\[(\d+)\]", r"B.\1.\2", bit), bit) for bit in sorted(other_config_groups[cfggrp])])
|
||
|
|
cfggrp = cfggrp.replace(" " + list(other_config_groups[cfggrp])[0], "")
|
||
|
|
print('<tr><td>%s</td><td>%s</td></tr>' % (cfggrp, bits))
|
||
|
|
print('</table></p>')
|
||
|
|
|
||
|
|
|
||
|
|
if outdir is not None:
|
||
|
|
stdout = sys.stdout
|
||
|
|
|
||
|
|
if not os.path.exists(outdir):
|
||
|
|
print("Creating %s/" % outdir, file=stdout)
|
||
|
|
os.makedirs(outdir)
|
||
|
|
|
||
|
|
print("Writing %s/index.html.." % outdir, file=stdout)
|
||
|
|
sys.stdout = open("%s/index.html" % outdir, "w")
|
||
|
|
print_index()
|
||
|
|
|
||
|
|
for x in range(ic.max_x+1):
|
||
|
|
for y in range(ic.max_y+1):
|
||
|
|
if (x, y) in mktiles:
|
||
|
|
print("Writing %s/tile_%d_%d.html.." % (outdir, x, y), file=stdout)
|
||
|
|
sys.stdout = open("%s/tile_%d_%d.html" % (outdir, x, y), "w")
|
||
|
|
print_tile(x, y)
|
||
|
|
|
||
|
|
print("Writing %s/chipdb.txt..." % outdir, file=stdout)
|
||
|
|
os.system("python icebox_chipdb.py > %s/chipdb.txt" % outdir)
|
||
|
|
|
||
|
|
sys.stdout = stdout
|
||
|
|
|
||
|
|
elif (tx, ty) == (0, 0):
|
||
|
|
print_index()
|
||
|
|
|
||
|
|
else:
|
||
|
|
print_tile(tx, ty)
|
||
|
|
|