Alan Mishchenko e5d8335268 Experiments with AIG-based simulation.

2017-12-05 09:49:02 -08:00

..

aig

Compiler warnings.

2017-07-22 11:41:17 +07:00

gia

Experiments with AIG-based simulation.

2017-12-05 09:49:02 -08:00

hop

Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes.

2017-12-03 14:39:11 -08:00

ioa

Bug fixes in the above patches.

2013-12-03 00:38:37 -08:00

ivy

Compiler warnings.

2017-07-22 11:41:17 +07:00

miniaig

Adding API to dump MiniAIG into a Verilog file and other small changes.

2017-10-22 15:44:13 -07:00

saig

Integrating Satoko into 'bmc' and 'bmc2'.

2017-08-16 14:20:52 +07:00