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103 lines
3.0 KiB
C
103 lines
3.0 KiB
C
/**CFile****************************************************************
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FileName [ioReadVerilog.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Command processing package.]
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Synopsis [Procedure to read network from file.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: ioReadVerilog.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "ioAbc.h"
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#include "base/ver/ver.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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//extern Abc_Des_t * Ver_ParseFile( char * pFileName, Abc_Des_t * pGateLib, int fCheck, int fUseMemMan );
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Reads hierarchical design from the Verilog file.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
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{
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Abc_Ntk_t * pNtk, * pTemp;
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Abc_Des_t * pDesign;
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int i, RetValue;
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// parse the verilog file
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pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 );
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if ( pDesign == NULL )
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return NULL;
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// detect top-level model
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RetValue = Abc_DesFindTopLevelModels( pDesign );
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pNtk = (Abc_Ntk_t *)Vec_PtrEntry( pDesign->vTops, 0 );
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if ( RetValue > 1 )
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{
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printf( "Warning: The design has %d root-level modules: ", Vec_PtrSize(pDesign->vTops) );
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Vec_PtrForEachEntry( Abc_Ntk_t *, pDesign->vTops, pTemp, i )
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printf( " %s", Abc_NtkName(pTemp) );
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printf( "\n" );
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printf( "The first one (%s) will be used.\n", pNtk->pName );
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}
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// extract the master network
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pNtk->pDesign = pDesign;
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pDesign->pManFunc = NULL;
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// verify the design for cyclic dependence
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assert( Vec_PtrSize(pDesign->vModules) > 0 );
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if ( Vec_PtrSize(pDesign->vModules) == 1 )
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{
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// printf( "Warning: The design is not hierarchical.\n" );
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Abc_DesFree( pDesign, pNtk );
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pNtk->pDesign = NULL;
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pNtk->pSpec = Extra_UtilStrsav( pFileName );
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}
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else
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{
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// check that there is no cyclic dependency
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Abc_NtkIsAcyclicHierarchy( pNtk );
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}
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//Io_WriteVerilog( pNtk, "_temp.v" );
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// Abc_NtkPrintBoxInfo( pNtk );
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return pNtk;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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