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mirror of https://github.com/YosysHQ/abc.git synced 2026-09-01 10:18:06 +02:00
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c3dccf3020e467da9fa62c9f609bce86b55ccd0a
abc/src/aig
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Alan Mishchenko c3dccf3020 Corner-case bug fixed in CNF generation.
2017-12-28 13:32:02 -08:00
..
aig
Compiler warnings.
2017-07-22 11:41:17 +07:00
gia
Corner-case bug fixed in CNF generation.
2017-12-28 13:32:02 -08:00
hop
Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes.
2017-12-03 14:39:11 -08:00
ioa
Bug fixes in the above patches.
2013-12-03 00:38:37 -08:00
ivy
Compiler warnings.
2017-07-22 11:41:17 +07:00
miniaig
Adding API to dump MiniAIG into a Verilog file and other small changes.
2017-10-22 15:44:13 -07:00
saig
Integrating Satoko into 'bmc' and 'bmc2'.
2017-08-16 14:20:52 +07:00
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