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mirror of https://github.com/YosysHQ/abc.git synced 2026-09-07 03:05:36 +02:00
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c3298ec22521bbc92326b2f3b996c13782df8f6a
abc/src/opt
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Alan Mishchenko c3298ec225 Improvements to the truth table computation in 'if' package.
2012-10-29 23:27:41 -07:00
..
cgt
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
csw
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
cut
Replacing 'st_table' by 'st__table' to resolve linker problems.
2012-09-29 17:11:03 -04:00
dar
Bug fix in XOR balancing (command 'balance -x').
2012-10-05 15:02:26 -07:00
dau
Improvements to the truth table computation in 'if' package.
2012-10-29 23:27:41 -07:00
fsim
Replacing Mb/Gb to be MB/GB.
2012-07-09 22:57:03 -07:00
fxu
Added an API to convert a multi-output PLA into a shared AIG.
2012-08-29 12:43:55 -07:00
lpk
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
mfs
Enabled recording the name of the file GIA is coming from.
2012-09-04 13:52:42 -07:00
nwk
Integrating GIA with LUT mapping.
2012-10-24 17:39:38 -07:00
res
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
ret
Replacing 'st_table' by 'st__table' to resolve linker problems.
2012-09-29 17:11:03 -04:00
rwr
Replacing 'st_table' by 'st__table' to resolve linker problems.
2012-09-29 17:11:03 -04:00
rwt
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
sim
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
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