mirror of https://github.com/YosysHQ/abc.git
132 lines
4.3 KiB
C
132 lines
4.3 KiB
C
/**CFile****************************************************************
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FileName [fraigEngine.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [And-Inverter Graph package.]
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Synopsis []
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: fraigEngine.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "aig.h"
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Starts the simulation engine for the first time.]
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Description [Tries several random patterns and their distance-1
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minterms hoping to get simulation started.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Aig_EngineSimulateFirst( Aig_Man_t * p )
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{
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Aig_Pattern_t * pPat;
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int i;
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assert( Vec_PtrSize(p->vPats) == 0 );
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for ( i = 0; i < p->nPatsMax; i++ )
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{
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pPat = Aig_PatternAlloc( Aig_ManPiNum(p) );
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Aig_PatternRandom( pPat );
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Vec_PtrPush( p->vPats, pPat );
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if ( !Aig_EngineSimulate( p ) )
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return;
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}
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}
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/**Function*************************************************************
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Synopsis [Implements intelligent simulation engine.]
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Description [Assumes that the good simulation patterns have been
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assigned (p->vPats). Simulates until all of them are gone. Returns 1
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if some classes are left. Returns 0 if there is no more classes.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Aig_EngineSimulate( Aig_Man_t * p )
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{
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Aig_Pattern_t * pPat;
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if ( Vec_VecSize(p->vClasses) == 0 )
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return 0;
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assert( Vec_PtrSize(p->vPats) > 0 );
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// process patterns
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while ( Vec_PtrSize(p->vPats) > 0 && Vec_VecSize(p->vClasses) > 0 )
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{
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// get the pattern and create new siminfo
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pPat = Vec_PtrPop(p->vPats);
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// create the new siminfo
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Aig_SimInfoFromPattern( p->pInfoPi, pPat );
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// free the patter
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Aig_PatternFree( pPat );
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// simulate this info
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Aig_ManSimulateInfo( p, p->pInfoPi, p->pInfoTemp );
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// split the classes and collect the new patterns
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Aig_ManUpdateClasses( p, p->pInfoTemp, p->vClasses );
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}
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return Vec_VecSize(p->vClasses) > 0;
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}
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/**Function*************************************************************
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Synopsis [Simulates all nodes using random simulation for the first time.]
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Description [Assigns the original simulation info and the storage for the
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future simulation info.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Aig_EngineSimulateRandomFirst( Aig_Man_t * p )
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{
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Aig_SimInfo_t * pInfoPi, * pInfoAll;
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assert( !p->pInfo && !p->pInfoTemp );
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// create random PI info
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pInfoPi = Aig_SimInfoAlloc( p->vPis->nSize, Aig_BitWordNum(p->pParam->nPatsRand), 0 );
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Aig_SimInfoRandom( pInfoPi );
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// allocate sim info for all nodes
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pInfoAll = Aig_SimInfoAlloc( p->vNodes->nSize, pInfoPi->nWords, 1 );
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// simulate though the circuit
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Aig_ManSimulateInfo( p, pInfoPi, pInfoAll );
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// detect classes
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p->vClasses = Aig_ManDeriveClassesFirst( p, pInfoAll );
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Aig_SimInfoFree( pInfoAll );
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// save simulation info
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p->pInfo = pInfoPi;
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p->pInfoPi = Aig_SimInfoAlloc( p->vPis->nSize, Aig_BitWordNum(p->vPis->nSize), 0 );
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p->pInfoTemp = Aig_SimInfoAlloc( p->vNodes->nSize, Aig_BitWordNum(p->vPis->nSize), 1 );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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