mirror of https://github.com/YosysHQ/abc.git
172 lines
5.4 KiB
C
172 lines
5.4 KiB
C
/**CFile****************************************************************
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FileName [fpgaTruth.c]
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PackageName [MVSIS 1.3: Multi-valued logic synthesis system.]
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Synopsis [Technology mapping for variable-size-LUT FPGAs.]
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Author [MVSIS Group]
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Affiliation [UC Berkeley]
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Date [Ver. 2.0. Started - August 18, 2004.]
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Revision [$Id: fpgaTruth.c,v 1.4 2005/01/23 06:59:42 alanmi Exp $]
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***********************************************************************/
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#include "fpgaInt.h"
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#include "bdd/cudd/cudd.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Recursively derives the truth table for the cut.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited )
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{
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DdNode * bFunc, * bFunc0, * bFunc1;
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assert( !Fpga_IsComplement(pCut) );
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// if the cut is visited, return the result
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if ( pCut->uSign )
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return (DdNode *)(ABC_PTRUINT_T)pCut->uSign;
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// compute the functions of the children
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bFunc0 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pOne), vVisited ); Cudd_Ref( bFunc0 );
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bFunc0 = Cudd_NotCond( bFunc0, Fpga_CutIsComplement(pCut->pOne) );
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bFunc1 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pTwo), vVisited ); Cudd_Ref( bFunc1 );
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bFunc1 = Cudd_NotCond( bFunc1, Fpga_CutIsComplement(pCut->pTwo) );
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// get the function of the cut
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bFunc = Cudd_bddAnd( dd, bFunc0, bFunc1 ); Cudd_Ref( bFunc );
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bFunc = Cudd_NotCond( bFunc, pCut->Phase );
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Cudd_RecursiveDeref( dd, bFunc0 );
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Cudd_RecursiveDeref( dd, bFunc1 );
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assert( pCut->uSign == 0 );
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pCut->uSign = (unsigned)(ABC_PTRUINT_T)bFunc;
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// add this cut to the visited list
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Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
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return bFunc;
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}
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/**Function*************************************************************
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Synopsis [Derives the truth table for one cut.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
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{
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Fpga_NodeVec_t * vVisited;
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DdNode * bFunc;
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int i;
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assert( pCut->nLeaves > 1 );
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// set the leaf variables
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for ( i = 0; i < pCut->nLeaves; i++ )
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pCut->ppLeaves[i]->pCuts->uSign = (unsigned)(ABC_PTRUINT_T)Cudd_bddIthVar( (DdManager *)dd, i );
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// recursively compute the function
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vVisited = Fpga_NodeVecAlloc( 10 );
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bFunc = Fpga_TruthsCutBdd_rec( (DdManager *)dd, pCut, vVisited ); Cudd_Ref( bFunc );
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// clean the intermediate BDDs
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for ( i = 0; i < pCut->nLeaves; i++ )
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pCut->ppLeaves[i]->pCuts->uSign = 0;
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for ( i = 0; i < vVisited->nSize; i++ )
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{
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pCut = (Fpga_Cut_t *)vVisited->pArray[i];
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Cudd_RecursiveDeref( (DdManager *)dd, (DdNode*)(ABC_PTRUINT_T)pCut->uSign );
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pCut->uSign = 0;
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}
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// printf( "%d ", vVisited->nSize );
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Fpga_NodeVecFree( vVisited );
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Cudd_Deref( bFunc );
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return bFunc;
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}
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/**Function*************************************************************
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Synopsis [Recursively derives the truth table for the cut.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Fpga_CutVolume_rec( Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited )
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{
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assert( !Fpga_IsComplement(pCut) );
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if ( pCut->fMark )
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return;
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pCut->fMark = 1;
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Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pOne), vVisited );
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Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pTwo), vVisited );
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Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
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}
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/**Function*************************************************************
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Synopsis [Derives the truth table for one cut.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Fpga_CutVolume( Fpga_Cut_t * pCut )
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{
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Fpga_NodeVec_t * vVisited;
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int Volume, i;
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assert( pCut->nLeaves > 1 );
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// set the leaf variables
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for ( i = 0; i < pCut->nLeaves; i++ )
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pCut->ppLeaves[i]->pCuts->fMark = 1;
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// recursively compute the function
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vVisited = Fpga_NodeVecAlloc( 10 );
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Fpga_CutVolume_rec( pCut, vVisited );
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// clean the marks
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for ( i = 0; i < pCut->nLeaves; i++ )
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pCut->ppLeaves[i]->pCuts->fMark = 0;
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for ( i = 0; i < vVisited->nSize; i++ )
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{
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pCut = (Fpga_Cut_t *)vVisited->pArray[i];
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pCut->fMark = 0;
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}
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Volume = vVisited->nSize;
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printf( "%d ", Volume );
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Fpga_NodeVecFree( vVisited );
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return Volume;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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