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mirror of https://github.com/YosysHQ/abc.git synced 2026-09-01 10:18:06 +02:00
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9e787c71919d63ef1a80a12eeb5abd954c7e86d8
abc/src/aig
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Alan Mishchenko 9e787c7191 Experiments with word-level retiming.
2018-09-30 20:51:37 -07:00
..
aig
Compiler warnings.
2017-07-22 11:41:17 +07:00
gia
Preserving output names while deriving a miter.
2018-09-20 14:34:59 -07:00
hop
Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes.
2017-12-03 14:39:11 -08:00
ioa
Bug fixes in the above patches.
2013-12-03 00:38:37 -08:00
ivy
Compiler warnings.
2017-07-22 11:41:17 +07:00
miniaig
Experiments with word-level retiming.
2018-09-30 20:51:37 -07:00
saig
Adding switch 'scorr -f' to dump inductive invariant as an AIG.
2018-03-22 10:10:09 -07:00
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