mirror of https://github.com/YosysHQ/abc.git
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/**CFile****************************************************************
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FileName [sswSimSat.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Inductive prover with constraints.]
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Synopsis [Performs resimulation using counter-examples.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - September 1, 2008.]
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Revision [$Id: sswSimSat.c,v 1.00 2008/09/01 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "sswInt.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Handle the counter-example.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Ssw_ManResimulateBit( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr )
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{
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Aig_Obj_t * pObj;
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int i, RetValue1, RetValue2;
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abctime clk = Abc_Clock();
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// set the PI simulation information
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Aig_ManConst1(p->pAig)->fMarkB = 1;
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Aig_ManForEachCi( p->pAig, pObj, i )
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pObj->fMarkB = Abc_InfoHasBit( p->pPatWords, i );
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// simulate internal nodes
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Aig_ManForEachNode( p->pAig, pObj, i )
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pObj->fMarkB = ( Aig_ObjFanin0(pObj)->fMarkB ^ Aig_ObjFaninC0(pObj) )
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& ( Aig_ObjFanin1(pObj)->fMarkB ^ Aig_ObjFaninC1(pObj) );
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// if repr is given, perform refinement
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if ( pRepr )
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{
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// check equivalence classes
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RetValue1 = Ssw_ClassesRefineConst1( p->ppClasses, 0 );
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RetValue2 = Ssw_ClassesRefine( p->ppClasses, 0 );
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// make sure refinement happened
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if ( Aig_ObjIsConst1(pRepr) )
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{
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assert( RetValue1 );
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if ( RetValue1 == 0 )
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Abc_Print( 1, "\nSsw_ManResimulateBit() Error: RetValue1 does not hold.\n" );
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}
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else
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{
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assert( RetValue2 );
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if ( RetValue2 == 0 )
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Abc_Print( 1, "\nSsw_ManResimulateBit() Error: RetValue2 does not hold.\n" );
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}
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}
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p->timeSimSat += Abc_Clock() - clk;
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}
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/**Function*************************************************************
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Synopsis [Handle the counter-example.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Ssw_ManResimulateWord( Ssw_Man_t * p, Aig_Obj_t * pCand, Aig_Obj_t * pRepr, int f )
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{
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int RetValue1, RetValue2;
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abctime clk = Abc_Clock();
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// set the PI simulation information
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Ssw_SmlAssignDist1Plus( p->pSml, p->pPatWords );
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// simulate internal nodes
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Ssw_SmlSimulateOne( p->pSml );
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// check equivalence classes
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RetValue1 = Ssw_ClassesRefineConst1( p->ppClasses, 1 );
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RetValue2 = Ssw_ClassesRefine( p->ppClasses, 1 );
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// make sure refinement happened
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if ( Aig_ObjIsConst1(pRepr) )
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{
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assert( RetValue1 );
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if ( RetValue1 == 0 )
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Abc_Print( 1, "\nSsw_ManResimulateWord() Error: RetValue1 does not hold.\n" );
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}
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else
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{
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assert( RetValue2 );
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if ( RetValue2 == 0 )
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Abc_Print( 1, "\nSsw_ManResimulateWord() Error: RetValue2 does not hold.\n" );
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}
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p->timeSimSat += Abc_Clock() - clk;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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