Alan Mishchenko 70a236379b Tuning LUT mapping flow.

2014-08-27 23:17:33 -07:00

..

abc

Added DSD-based collapsing &dsd.

2014-08-16 11:54:49 -07:00

abci

Tuning LUT mapping flow.

2014-08-27 23:17:33 -07:00

cmd

Adding barrier buffers.

2014-03-16 21:56:28 -07:00

io

Compiler warning.

2014-08-27 23:03:39 -07:00

main

Improvements to DSD balancing.

2014-08-27 12:23:31 -07:00

test

Updating project settings to have simpler include paths.

2012-07-07 20:14:12 -07:00

ver

Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, such as [7:7], which seems to help in some cases.

2014-08-02 17:00:24 -07:00