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393 lines
21 KiB
C
393 lines
21 KiB
C
/**CFile****************************************************************
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FileName [fpgaInt.h]
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PackageName [MVSIS 2.0: Multi-valued logic synthesis system.]
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Synopsis [Technology mapping for variable-size-LUT FPGAs.]
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Author [MVSIS Group]
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Affiliation [UC Berkeley]
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Date [Ver. 2.0. Started - August 18, 2004.]
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Revision [$Id: fpgaInt.h,v 1.8 2004/09/30 21:18:10 satrajit Exp $]
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***********************************************************************/
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#ifndef __FPGA_INT_H__
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#define __FPGA_INT_H__
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////////////////////////////////////////////////////////////////////////
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/// INCLUDES ///
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////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "extra.h"
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#include "fpga.h"
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ABC_NAMESPACE_HEADER_START
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////////////////////////////////////////////////////////////////////////
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/// PARAMETERS ///
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////////////////////////////////////////////////////////////////////////
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// uncomment to have fanouts represented in the mapping graph
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//#define FPGA_ALLOCATE_FANOUT 1
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////////////////////////////////////////////////////////////////////////
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/// MACRO DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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#ifdef _WIN32
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#define inline __inline // compatible with MS VS 6.0
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#endif
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// the maximum number of cut leaves (currently does not work for 7)
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#define FPGA_MAX_LEAVES 6
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// the bit masks
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#define FPGA_MASK(n) ((~((unsigned)0)) >> (32-(n)))
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#define FPGA_FULL (~((unsigned)0))
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#define FPGA_NO_VAR (-9999.0)
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#define FPGA_NUM_BYTES(n) (((n)/16 + (((n)%16) > 0))*16)
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// maximum/minimum operators
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#define FPGA_MIN(a,b) (((a) < (b))? (a) : (b))
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#define FPGA_MAX(a,b) (((a) > (b))? (a) : (b))
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// the small and large numbers (min/max float are 1.17e-38/3.40e+38)
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#define FPGA_FLOAT_LARGE ((float)1.0e+20)
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#define FPGA_FLOAT_SMALL ((float)1.0e-20)
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#define FPGA_INT_LARGE (10000000)
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// the macro to compute the signature
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#define FPGA_SEQ_SIGN(p) (1 << (((ABC_PTRUINT_T)p)%31));
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// internal macros to work with cuts
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#define Fpga_CutIsComplement(p) (((int)((ABC_PTRUINT_T)(p) & 01)))
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#define Fpga_CutRegular(p) ((Fpga_Cut_t *)((ABC_PTRUINT_T)(p) & ~01))
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#define Fpga_CutNot(p) ((Fpga_Cut_t *)((ABC_PTRUINT_T)(p) ^ 01))
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#define Fpga_CutNotCond(p,c) ((Fpga_Cut_t *)((ABC_PTRUINT_T)(p) ^ (c)))
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// the cut nodes
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#define Fpga_SeqIsComplement( p ) (((int)((ABC_PTRUINT_T) (p) & 01)))
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#define Fpga_SeqRegular( p ) ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) & ~015))
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#define Fpga_SeqIndex( p ) ((((ABC_PTRUINT_T)(p)) >> 1) & 07)
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#define Fpga_SeqIndexCreate( p, Ind ) (((ABC_PTRUINT_T)(p)) | (1 << (((ABC_PTRUINT_T)(Ind)) & 07)))
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// internal macros for referencing of nodes
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#define Fpga_NodeReadRef(p) ((Fpga_Regular(p))->nRefs)
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#define Fpga_NodeRef(p) ((Fpga_Regular(p))->nRefs++)
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// returns the complemented attribute of the node
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#define Fpga_NodeIsSimComplement(p) (Fpga_IsComplement(p)? !(Fpga_Regular(p)->fInv) : (p)->fInv)
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// generating random unsigned (#define RAND_MAX 0x7fff)
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#define FPGA_RANDOM_UNSIGNED ((((unsigned)rand()) << 24) ^ (((unsigned)rand()) << 12) ^ ((unsigned)rand()))
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////////////////////////////////////////////////////////////////////////
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/// STRUCTURE DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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// the mapping manager
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struct Fpga_ManStruct_t_
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{
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// the mapping graph
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Fpga_Node_t ** pBins; // the table of nodes hashed by their children
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int nBins; // the size of the table
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Fpga_Node_t ** pInputs; // the array of inputs
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int nInputs; // the number of inputs
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Fpga_Node_t ** pOutputs; // the array of outputs
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int nOutputs; // the number of outputs
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int nNodes; // the total number of nodes
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int nLatches; // the number of latches in the circuit
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Fpga_Node_t * pConst1; // the constant 1 node
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Fpga_NodeVec_t * vNodesAll; // the nodes by number
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Fpga_NodeVec_t * vAnds; // the nodes reachable from COs
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Fpga_NodeVec_t * vMapping; // the nodes used in the current mapping
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// info about the original circuit
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char * pFileName; // the file name
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char ** ppOutputNames; // the primary output names
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float * pInputArrivals;// the PI arrival times
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// mapping parameters
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int nVarsMax; // the max number of variables
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int fAreaRecovery; // the flag to use area flow as the first parameter
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int fVerbose; // the verbosiness flag
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int fSwitching; // minimize the switching activity (instead of area)
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int fLatchPaths; // optimize latch paths for delay, other paths for area
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int nTravIds; // the counter of traversal IDs
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float DelayTarget; // the target required times
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// support of choice nodes
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int nChoiceNodes; // the number of choice nodes
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int nChoices; // the number of all choices
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int nCanons;
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int nMatches;
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// the supergate library
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Fpga_LutLib_t * pLutLib; // the current LUT library
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// the memory managers
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Extra_MmFixed_t * mmNodes; // the memory manager for nodes
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Extra_MmFixed_t * mmCuts; // the memory manager for cuts
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// resynthesis parameters
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int fResynthesis; // the resynthesis flag
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float fRequiredGlo; // the global required times
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float fRequiredShift;// the shift of the required times
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float fRequiredStart;// the starting global required times
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float fRequiredGain; // the reduction in delay
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float fAreaGlo; // the total area
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float fAreaGain; // the reduction in area
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float fEpsilon; // the epsilon used to compare floats
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float fDelayWindow; // the delay window for delay-oriented resynthesis
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float DelayLimit; // for resynthesis
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float AreaLimit; // for resynthesis
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float TimeLimit; // for resynthesis
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// runtime statistics
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int timeToMap; // time to transfer to the mapping structure
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int timeCuts; // time to compute k-feasible cuts
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int timeTruth; // time to compute the truth table for each cut
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int timeMatch; // time to perform matching for each node
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int timeRecover; // time to perform area recovery
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int timeToNet; // time to transfer back to the network
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int timeTotal; // the total mapping time
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int time1; // time to transfer to the mapping structure
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int time2; // time to transfer to the mapping structure
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};
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// the LUT library
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struct Fpga_LutLibStruct_t_
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{
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char * pName; // the name of the LUT library
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int LutMax; // the maximum LUT size
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int fVarPinDelays; // set to 1 if variable pin delays are specified
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float pLutAreas[FPGA_MAX_LUTSIZE+1]; // the areas of LUTs
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float pLutDelays[FPGA_MAX_LUTSIZE+1][FPGA_MAX_LUTSIZE+1];// the delays of LUTs
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};
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// the mapping node
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struct Fpga_NodeStruct_t_
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{
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// general information about the node
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Fpga_Node_t * pNext; // the next node in the hash table
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Fpga_Node_t * pLevel; // the next node in the linked list by level
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int Num; // the unique number of this node
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int NumA; // the unique number of this node
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int Num2; // the temporary number of this node
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int nRefs; // the number of references (fanouts) of the given node
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unsigned fMark0 : 1; // the mark used for traversals
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unsigned fMark1 : 1; // the mark used for traversals
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unsigned fInv : 1; // the complemented attribute for the equivalent nodes
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unsigned Value : 2; // the value of the nodes
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unsigned fUsed : 1; // the flag indicating that the node is used in the mapping
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unsigned fTemp : 1; // unused
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unsigned Level :11; // the level of the given node
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unsigned uData :14; // used to mark the fanins, for which resynthesis was tried
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int TravId;
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// the successors of this node
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Fpga_Node_t * p1; // the first child
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Fpga_Node_t * p2; // the second child
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Fpga_Node_t * pNextE; // the next functionally equivalent node
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Fpga_Node_t * pRepr; // the representative of the functionally equivalent class
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#ifdef FPGA_ALLOCATE_FANOUT
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// representation of node's fanouts
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Fpga_Node_t * pFanPivot; // the first fanout of this node
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Fpga_Node_t * pFanFanin1; // the next fanout of p1
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Fpga_Node_t * pFanFanin2; // the next fanout of p2
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// Fpga_NodeVec_t * vFanouts; // the array of fanouts of the gate
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#endif
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// the delay information
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float tRequired; // the best area flow
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float aEstFanouts; // the fanout estimation
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float Switching; // the probability of switching
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int LValue; // the l-value of the node
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short nLatches1; // the number of latches on the first edge
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short nLatches2; // the number of latches on the second edge
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// cut information
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Fpga_Cut_t * pCutBest; // the best mapping
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Fpga_Cut_t * pCutOld; // the old mapping
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Fpga_Cut_t * pCuts; // mapping choices for the node (elementary comes first)
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Fpga_Cut_t * pCutsN; // mapping choices for the node (elementary comes first)
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// misc information
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char * pData0; // temporary storage for the corresponding network node
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};
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// the cuts used for matching
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struct Fpga_CutStruct_t_
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{
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Fpga_Cut_t * pOne; // the father of this cut
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Fpga_Cut_t * pTwo; // the mother of this cut
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Fpga_Node_t * pRoot; // the root of the cut
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Fpga_Node_t * ppLeaves[FPGA_MAX_LEAVES+1]; // the leaves of this cut
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float fLevel; // the average level of the fanins
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unsigned uSign; // signature for quick comparison
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char fMark; // the mark to denote visited cut
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char Phase; // the mark to denote complemented cut
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char nLeaves; // the number of leaves of this cut
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char nVolume; // the volume of this cut
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float tArrival; // the arrival time
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float aFlow; // the area flow of the cut
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Fpga_Cut_t * pNext; // the pointer to the next cut in the list
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};
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// the vector of nodes
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struct Fpga_NodeVecStruct_t_
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{
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Fpga_Node_t ** pArray; // the array of nodes
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int nSize; // the number of entries in the array
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int nCap; // the number of allocated entries
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};
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// getting hold of the next fanout of the node
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#define Fpga_NodeReadNextFanout( pNode, pFanout ) \
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( ( pFanout == NULL )? NULL : \
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((Fpga_Regular((pFanout)->p1) == (pNode))? \
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(pFanout)->pFanFanin1 : (pFanout)->pFanFanin2) )
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// getting hold of the place where the next fanout will be attached
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#define Fpga_NodeReadNextFanoutPlace( pNode, pFanout ) \
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( (Fpga_Regular((pFanout)->p1) == (pNode))? \
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&(pFanout)->pFanFanin1 : &(pFanout)->pFanFanin2 )
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// iterator through the fanouts of the node
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#define Fpga_NodeForEachFanout( pNode, pFanout ) \
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for ( pFanout = (pNode)->pFanPivot; pFanout; \
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pFanout = Fpga_NodeReadNextFanout(pNode, pFanout) )
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// safe iterator through the fanouts of the node
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#define Fpga_NodeForEachFanoutSafe( pNode, pFanout, pFanout2 ) \
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for ( pFanout = (pNode)->pFanPivot, \
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pFanout2 = Fpga_NodeReadNextFanout(pNode, pFanout); \
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pFanout; \
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pFanout = pFanout2, \
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pFanout2 = Fpga_NodeReadNextFanout(pNode, pFanout) )
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static inline int Fpga_FloatMoreThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 > Arg2 + p->fEpsilon; }
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static inline int Fpga_FloatLessThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 < Arg2 - p->fEpsilon; }
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static inline int Fpga_FloatEqual( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 > Arg2 - p->fEpsilon && Arg1 < Arg2 + p->fEpsilon; }
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////////////////////////////////////////////////////////////////////////
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/// GLOBAL VARIABLES ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/*=== fpgaCut.c ===============================================================*/
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extern void Fpga_MappingCuts( Fpga_Man_t * p );
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extern void Fpga_MappingCreatePiCuts( Fpga_Man_t * p );
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extern int Fpga_CutCountAll( Fpga_Man_t * pMan );
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/*=== fpgaCutUtils.c ===============================================================*/
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extern Fpga_Cut_t * Fpga_CutAlloc( Fpga_Man_t * p );
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extern Fpga_Cut_t * Fpga_CutDup( Fpga_Man_t * p, Fpga_Cut_t * pCutOld );
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extern void Fpga_CutFree( Fpga_Man_t * p, Fpga_Cut_t * pCut );
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extern void Fpga_CutPrint( Fpga_Man_t * p, Fpga_Node_t * pRoot, Fpga_Cut_t * pCut );
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extern Fpga_Cut_t * Fpga_CutCreateSimple( Fpga_Man_t * p, Fpga_Node_t * pNode );
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extern float Fpga_CutGetRootArea( Fpga_Man_t * p, Fpga_Cut_t * pCut );
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extern Fpga_Cut_t * Fpga_CutListAppend( Fpga_Cut_t * pSetAll, Fpga_Cut_t * pSets );
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extern void Fpga_CutListRecycle( Fpga_Man_t * p, Fpga_Cut_t * pSetList, Fpga_Cut_t * pSave );
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extern int Fpga_CutListCount( Fpga_Cut_t * pSets );
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extern void Fpga_CutRemoveFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut );
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extern void Fpga_CutInsertFanouts( Fpga_Man_t * p, Fpga_Node_t * pNode, Fpga_Cut_t * pCut );
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extern float Fpga_CutGetAreaRefed( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
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extern float Fpga_CutGetAreaDerefed( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
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extern float Fpga_CutRef( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
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extern float Fpga_CutDeref( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
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extern float Fpga_CutGetAreaFlow( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
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extern void Fpga_CutGetParameters( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
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/*=== fraigFanout.c =============================================================*/
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extern void Fpga_NodeAddFaninFanout( Fpga_Node_t * pFanin, Fpga_Node_t * pFanout );
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extern void Fpga_NodeRemoveFaninFanout( Fpga_Node_t * pFanin, Fpga_Node_t * pFanoutToRemove );
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extern int Fpga_NodeGetFanoutNum( Fpga_Node_t * pNode );
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/*=== fpgaLib.c ============================================================*/
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extern Fpga_LutLib_t * Fpga_LutLibRead( char * FileName, int fVerbose );
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extern void Fpga_LutLibFree( Fpga_LutLib_t * p );
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extern void Fpga_LutLibPrint( Fpga_LutLib_t * pLutLib );
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extern int Fpga_LutLibDelaysAreDiscrete( Fpga_LutLib_t * pLutLib );
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/*=== fpgaMatch.c ===============================================================*/
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extern int Fpga_MappingMatches( Fpga_Man_t * p, int fDelayOriented );
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extern int Fpga_MappingMatchesArea( Fpga_Man_t * p );
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extern int Fpga_MappingMatchesSwitch( Fpga_Man_t * p );
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/*=== fpgaShow.c =============================================================*/
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extern void Fpga_MappingShow( Fpga_Man_t * pMan, char * pFileName );
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extern void Fpga_MappingShowNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppRoots, int nRoots, char * pFileName );
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/*=== fpgaSwitch.c =============================================================*/
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extern float Fpga_CutGetSwitchDerefed( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut );
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extern float Fpga_CutRefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
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extern float Fpga_CutDerefSwitch( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts );
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extern float Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeVec_t * vMapping );
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/*=== fpgaTime.c ===============================================================*/
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extern float Fpga_TimeCutComputeArrival( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
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extern float Fpga_TimeCutComputeArrival_rec( Fpga_Man_t * pMan, Fpga_Cut_t * pCut );
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extern float Fpga_TimeComputeArrivalMax( Fpga_Man_t * p );
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extern void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p, int fFirstTime );
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extern void Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired );
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extern void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
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extern void Fpga_TimePropagateArrival( Fpga_Man_t * p );
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/*=== fpgaVec.c =============================================================*/
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extern Fpga_NodeVec_t * Fpga_NodeVecAlloc( int nCap );
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extern void Fpga_NodeVecFree( Fpga_NodeVec_t * p );
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extern Fpga_Node_t ** Fpga_NodeVecReadArray( Fpga_NodeVec_t * p );
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extern int Fpga_NodeVecReadSize( Fpga_NodeVec_t * p );
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extern void Fpga_NodeVecGrow( Fpga_NodeVec_t * p, int nCapMin );
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extern void Fpga_NodeVecShrink( Fpga_NodeVec_t * p, int nSizeNew );
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extern void Fpga_NodeVecClear( Fpga_NodeVec_t * p );
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extern void Fpga_NodeVecPush( Fpga_NodeVec_t * p, Fpga_Node_t * Entry );
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extern int Fpga_NodeVecPushUnique( Fpga_NodeVec_t * p, Fpga_Node_t * Entry );
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extern Fpga_Node_t * Fpga_NodeVecPop( Fpga_NodeVec_t * p );
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extern void Fpga_NodeVecWriteEntry( Fpga_NodeVec_t * p, int i, Fpga_Node_t * Entry );
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extern Fpga_Node_t * Fpga_NodeVecReadEntry( Fpga_NodeVec_t * p, int i );
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extern void Fpga_NodeVecSortByLevel( Fpga_NodeVec_t * p );
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extern void Fpga_SortNodesByArrivalTimes( Fpga_NodeVec_t * p );
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extern void Fpga_NodeVecUnion( Fpga_NodeVec_t * p, Fpga_NodeVec_t * p1, Fpga_NodeVec_t * p2 );
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extern void Fpga_NodeVecPushOrder( Fpga_NodeVec_t * vNodes, Fpga_Node_t * pNode, int fIncreasing );
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extern void Fpga_NodeVecReverse( Fpga_NodeVec_t * vNodes );
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/*=== fpgaUtils.c ===============================================================*/
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extern Fpga_NodeVec_t * Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv );
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extern Fpga_NodeVec_t * Fpga_MappingDfsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppNodes, int nNodes, int fEquiv );
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extern int Fpga_CountLevels( Fpga_Man_t * pMan );
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extern float Fpga_MappingGetAreaFlow( Fpga_Man_t * p );
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extern float Fpga_MappingArea( Fpga_Man_t * pMan );
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extern float Fpga_MappingAreaTrav( Fpga_Man_t * pMan );
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extern float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan );
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extern void Fpga_MappingPrintOutputArrivals( Fpga_Man_t * p );
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extern void Fpga_MappingSetupTruthTables( unsigned uTruths[][2] );
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extern void Fpga_MappingSetupMask( unsigned uMask[], int nVarsMax );
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extern void Fpga_MappingSortByLevel( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes, int fIncreasing );
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extern Fpga_NodeVec_t * Fpga_DfsLim( Fpga_Man_t * pMan, Fpga_Node_t * pNode, int nLevels );
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extern Fpga_NodeVec_t * Fpga_MappingLevelize( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes );
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extern int Fpga_MappingMaxLevel( Fpga_Man_t * pMan );
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extern void Fpga_ManReportChoices( Fpga_Man_t * pMan );
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extern void Fpga_MappingSetChoiceLevels( Fpga_Man_t * pMan );
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/*=== CUDD package.c ===============================================================*/
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extern unsigned int Cudd_Prime( unsigned int p );
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ABC_NAMESPACE_HEADER_END
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#endif
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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