mirror of https://github.com/YosysHQ/abc.git
97 lines
5.7 KiB
Plaintext
97 lines
5.7 KiB
Plaintext
UC Berkeley, ABC 1.01 (compiled Feb 3 2006 10:48:34)
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abc 01> so regtest.script
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abc - > r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps
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Networks are equivalent after fraiging.
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examples/apex4: i/o = 9/ 19 lat = 0 nd = 1185 cube = 2200 lev = 7
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The shared BDD size is 900 nodes.
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A simple supergate library is derived from gate library "mcnc_temp.genlib".
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Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.03 sec
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Networks are equivalent after fraiging.
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examples/apex4: i/o = 9/ 19 lat = 0 nd = 1837 area = 4560.00 delay = 11.70 lev = 11
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abc - > r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps
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Networks are equivalent after fraiging.
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C2670.iscas : i/o = 233/ 140 lat = 0 nd = 218 cube = 444 lev = 7
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Networks are equivalent after fraiging.
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C2670.iscas : i/o = 233/ 140 lat = 0 nd = 466 area = 1160.00 delay = 15.50 lev = 14
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abc - > r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps
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Networks are equivalent after fraiging.
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The shared BDD size is 1111 nodes.
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Networks are equivalent after fraiging.
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frg2 : i/o = 143/ 139 lat = 0 nd = 547 area = 1381.00 delay = 9.70 lev = 9
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abc - > r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps
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Networks are equivalent after fraiging.
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exCombCkt : i/o = 1769/1063 lat = 0 nd = 5609 cube = 10395 lev = 15
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Networks are equivalent after fraiging.
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exCombCkt : i/o = 1769/1063 lat = 0 nd = 10317 area = 24980.00 delay = 29.80 lev = 27
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abc - > r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps
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Networks are equivalent after fraiging.
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examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4405 cube = 7515 lev = 9
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Networks are equivalent after fraiging.
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examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8509 area = 19316.00 delay = 20.60 lev = 17
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abc - > r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps
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Networks are equivalent after fraiging.
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ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4085 cube = 7780 lev = 4
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Networks are equivalent after fraiging.
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ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8278 area = 19714.00 delay = 8.10 lev = 8
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abc - > r examples/s444.blif; b; esd -v; dsd; cec; ps
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The shared BDD size is 181 nodes.
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BDD nodes in the transition relation before reordering 557.
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BDD nodes in the transition relation after reordering 456.
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Reachability analysis completed in 151 iterations.
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The number of minterms in the reachable state set = 8865.
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BDD nodes in the unreachable states before reordering 124.
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BDD nodes in the unreachable states after reordering 113.
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Networks are equivalent after fraiging.
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s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7
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abc - > r examples/i10.blif; fpga; cec; ps; u; map; cec; ps
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The network was strashed and balanced before FPGA mapping.
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Networks are equivalent after fraiging.
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i10 : i/o = 257/ 224 lat = 0 nd = 899 cube = 1604 lev = 13
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The network was strashed and balanced before mapping.
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Networks are equivalent after fraiging.
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i10 : i/o = 257/ 224 lat = 0 nd = 1676 area = 4219.00 delay = 30.80 lev = 29
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abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps
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The number of AIG nodes added to storage = 2675.
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The number of AIG nodes added to storage = 1744.
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The number of AIG nodes added to storage = 1431.
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Currently stored 3 networks with 5850 nodes will be fraiged.
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Performing FPGA mapping with choices.
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Networks are equivalent after fraiging.
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i10 : i/o = 257/ 224 lat = 0 nd = 792 cube = 1459 lev = 12
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Performing mapping with choices.
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Networks are equivalent after fraiging.
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i10 : i/o = 257/ 224 lat = 0 nd = 1484 area = 3518.00 delay = 25.60 lev = 23
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abc - > r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec
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The network was strashed and balanced before FPGA mapping.
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s6669 : i/o = 83/ 55 lat = 239 nd = 679 bdd = 3046 lev = 20
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Networks are equivalent after fraiging.
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The network was strashed and balanced before FPGA mapping/retiming.
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The number of MUXes detected = 120 (34.25 % of logic). Creating solver = 0.00 sec
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SAT solver time = 0.00 sec
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The number of LUTs with incompatible edges = 24.
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The number of LUTs with more than 4 inputs = 18.
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s6669 : i/o = 83/ 55 lat = 404 nd = 818 bdd = 3829 lev = 6
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Networks are equivalent after fraiging.
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The network was strashed and balanced before FPGA mapping.
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The number of MUXes detected = 69 (37.03 % of logic). Creating solver = 0.00 sec
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SAT solver time = 0.00 sec
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s6669 : i/o = 83/ 55 lat = 346 nd = 772 bdd = 3254 lev = 9
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Networks are equivalent after fraiging.
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abc - > r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec
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The network was strashed and balanced before mapping.
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s5378 : i/o = 35/ 49 lat = 164 nd = 1015 area = 2384.00 delay = 12.40 lev = 10
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Networks are equivalent after fraiging.
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The number of nodes with equal fanins = 5.
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The network was strashed and balanced before SC mapping/retiming.
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The mininum clock period computed is 10.00.
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The resulting network is derived as BDD logic network (this is temporary).
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The number of MUXes detected = 0 ( 0.00 % of logic). Creating solver = 0.00 sec
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SAT solver time = 0.00 sec
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s5378 : i/o = 35/ 49 lat = 396 nd = 1252 bdd = 4612 lev = 7
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Networks are equivalent after fraiging.
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The network was strashed and balanced before mapping.
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s5378 : i/o = 35/ 49 lat = 360 nd = 1087 area = 2454.00 delay = 12.10 lev = 11
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Networks are equivalent after fraiging.
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abc - > time
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elapse: 39.54 seconds, total: 39.54 seconds
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abc 122> |