Alan Mishchenko 2e8543fca1 Adding names to GIA inputs/outputs. Changing polarity of invariant generated by PDR.

2015-12-21 23:22:17 -10:00

..

module.make

Sequential word-level simulator for Wlc_Ntk_t.

2015-06-04 22:32:51 -07:00

wlc.c

Verilog benchmark generation code.

2015-07-15 00:21:26 -07:00

wlc.h

Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling printout of AND2 in '%ps -d'.

2015-07-16 17:37:48 -07:00

wlcAbs.c

Merging two branches.

2014-11-17 18:03:51 -08:00

wlcBlast.c

Adding names to GIA inputs/outputs. Changing polarity of invariant generated by PDR.

2015-12-21 23:22:17 -10:00

wlcCom.c

Corner-case bug in invariant profiling.

2015-12-18 12:25:24 -10:00

wlcNtk.c

Changes to be able to compile ABC without CUDD.

2015-08-24 19:49:18 -07:00

wlcReadSmt.c

Fix C++ compilation errors

2015-10-16 14:02:30 -07:00

wlcReadVer.c

Adding code to support gate profiles.

2015-12-14 00:44:33 -08:00

wlcSim.c

C++ compiler typecast problem.

2015-07-08 15:04:26 -07:00

wlcStdin.c

Support for representing programmable cell configuration data.

2015-03-08 20:17:59 -07:00

wlcWriteVer.c

Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator (@).

2015-07-14 19:55:05 -07:00