mirror of https://github.com/YosysHQ/abc.git
56 lines
1.8 KiB
Plaintext
56 lines
1.8 KiB
Plaintext
Minor things:
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- add required time support
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- clean end-of-line markers (CR is more preferable than CR-LF)
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- prevent node name clash between PO and internal names (i.e. [484])
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- add the output of ABC version/platform in the output files
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- fix gcc compiler warnings
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Major things:
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- substantially improving performance of FRAIGing
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(used in equivalence checking and lossless synthesis)
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- developing a new (more efficient and faster) AIG rewriting package
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- implementing additional rewriting options for delay optimization
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- making technology mapping applicable to very large designs by adding
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on-demand cut computation currenlty available as a stand-alone command "cut"
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- experimenting with yield-aware standard-cell mapping
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- developing a mapper for arbitrary programmable macrocell
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architecture specified using a configuration file (this mapper should work
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for both cell-evalution and mainstream FPGA mapping)
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- developing incremental retiming and incremental integrated sequential
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synthesis
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- developing sequential verification combined with integrated sequential
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synthesis
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Other great projects:
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- hierarchical BLIF input in ABC (output of black boxes)
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- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
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- incremental retiming and sequential integration
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- 5-6 input AIG rewriting using new ideas
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- placement-aware mapping
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- mapping into MV cells
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- better ways of constructing BDDs
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- SAT solver with linear constraints
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- specialized synthesis for EXORs and large MUXes
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- sequential AIG rewriting
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Other:
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- completely silent mode
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High-priority changes:
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- add a new mode to "fpga" to differentiate latch-to-latch and pad-to-latch paths
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- support asynchronous set/reset in retiming and retiming/mapping
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- port "mfs" into ABC
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- reduce the latch count in the new version of "retime" and "spfga" |