mirror of https://github.com/YosysHQ/abc.git
124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
/**CFile****************************************************************
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FileName [llb2Map.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [BDD based reachability.]
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Synopsis [Non-linear quantification scheduling.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: llb2Map.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "llbInt.h"
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#include "base/abc/abc.h"
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#include "map/if/if.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Returns internal nodes used in the mapping.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Int_t * Llb_AigMap( Aig_Man_t * pAig, int nLutSize, int nLutMin )
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{
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extern Abc_Ntk_t * Abc_NtkFromAigPhase( Aig_Man_t * pMan );
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extern If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
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extern void Gia_ManSetIfParsDefault( void * pPars );
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If_Par_t Pars, * pPars = &Pars;
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If_Man_t * pIfMan;
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If_Obj_t * pAnd;
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Abc_Ntk_t * pNtk;
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Abc_Obj_t * pNode;
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Vec_Int_t * vNodes;
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Aig_Obj_t * pObj;
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int i;
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// create ABC network
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pNtk = Abc_NtkFromAigPhase( pAig );
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assert( Abc_NtkIsStrash(pNtk) );
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// derive mapping parameters
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Gia_ManSetIfParsDefault( pPars );
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pPars->nLutSize = nLutSize;
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// get timing information
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pPars->pTimesArr = Abc_NtkGetCiArrivalFloats(pNtk);
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pPars->pTimesReq = Abc_NtkGetCoRequiredFloats(pNtk);
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// perform LUT mapping
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pIfMan = Abc_NtkToIf( pNtk, pPars );
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if ( pIfMan == NULL )
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{
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Abc_NtkDelete( pNtk );
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return NULL;
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}
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if ( !If_ManPerformMapping( pIfMan ) )
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{
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Abc_NtkDelete( pNtk );
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If_ManStop( pIfMan );
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return NULL;
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}
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// mark nodes in the AIG used in the mapping
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Aig_ManCleanMarkA( pAig );
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Aig_ManForEachNode( pAig, pObj, i )
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{
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pNode = (Abc_Obj_t *)pObj->pData;
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if ( pNode == NULL )
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continue;
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pAnd = (If_Obj_t *)pNode->pCopy;
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if ( pAnd == NULL )
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continue;
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if ( pAnd->nRefs > 0 && (int)If_ObjCutBest(pAnd)->nLeaves >= nLutMin )
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pObj->fMarkA = 1;
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}
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Abc_NtkDelete( pNtk );
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If_ManStop( pIfMan );
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// unmark flop drivers
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Saig_ManForEachLi( pAig, pObj, i )
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Aig_ObjFanin0(pObj)->fMarkA = 0;
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// collect mapping
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vNodes = Vec_IntAlloc( 100 );
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Aig_ManForEachNode( pAig, pObj, i )
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if ( pObj->fMarkA )
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Vec_IntPush( vNodes, Aig_ObjId(pObj) );
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Aig_ManCleanMarkA( pAig );
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return vNodes;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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