mirror of https://github.com/YosysHQ/abc.git
114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
/**CFile****************************************************************
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FileName [rewireMap.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewireMap.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "rewireMap.h"
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ABC_NAMESPACE_IMPL_START
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extern Abc_Ntk_t *Abc_NtkFromAigPhase(Aig_Man_t *pMan);
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extern Abc_Ntk_t *Abc_NtkDarAmap(Abc_Ntk_t *pNtk, Amap_Par_t *pPars);
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extern Abc_Ntk_t * Abc_NtkDch( Abc_Ntk_t * pNtk, Dch_Pars_t * pPars );
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extern void *Abc_FrameReadLibGen2();
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extern Vec_Int_t * Abc_NtkWriteMiniMapping( Abc_Ntk_t * pNtk );
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extern void Abc_NtkPrintMiniMapping( int * pArray );
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extern Abc_Ntk_t * Abc_NtkFromMiniMapping( int *vMapping );
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extern Mini_Aig_t * Abc_MiniAigFromNtk ( Abc_Ntk_t *pNtk );
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extern void Nf_ManSetDefaultPars( Jf_Par_t * pPars );
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extern Gia_Man_t * Nf_ManPerformMapping( Gia_Man_t * pGia, Jf_Par_t * pPars );
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extern Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p, int fFindEnables, int fUseBuffs );
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extern Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p, int fUseBuffs );
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extern int Gia_ManSimpleMapping( Gia_Man_t * p, int nBound, int Seed, int nBTLimit, int nTimeout, int fVerbose, int fKeepFile, int argc, char ** argv );
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Abc_Ntk_t *Gia_ManRewirePut(Gia_Man_t *pGia) {
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Aig_Man_t *pMan = Gia_ManToAig(pGia, 0);
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Abc_Ntk_t *pNtk = Abc_NtkFromAigPhase(pMan);
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Abc_NtkSetName(pNtk, Abc_UtilStrsav(Gia_ManName(pGia)));
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Aig_ManStop(pMan);
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return pNtk;
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}
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Abc_Ntk_t *Abc_ManRewireDch(Abc_Ntk_t *pNtk) {
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Dch_Pars_t Pars, *pPars = &Pars;
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Dch_ManSetDefaultParams(pPars);
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pNtk = Abc_NtkDch(pNtk, pPars);
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if (pNtk == NULL) {
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Abc_Print(-1, "Dch compute has failed.\n");
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return NULL;
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}
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return pNtk;
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}
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Gia_Man_t *Gia_ManRewireDch(Gia_Man_t *pGia) {
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Dch_Pars_t Pars, *pPars = &Pars;
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Dch_ManSetDefaultParams(pPars);
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pGia = Gia_ManPerformDch( pGia, pPars );
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if (pGia == NULL) {
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Abc_Print(-1, "Dch compute has failed.\n");
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return NULL;
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}
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return pGia;
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}
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Abc_Ntk_t *Abc_ManRewireMapAmap(Abc_Ntk_t *pNtk) {
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Amap_Par_t Pars, *pPars = &Pars;
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Amap_ManSetDefaultParams(pPars);
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Abc_Ntk_t *pNtkMapped = Abc_NtkDarAmap(pNtk, pPars);
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if (pNtkMapped == NULL) {
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Abc_Print(-1, "Mapping has failed.\n");
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return NULL;
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}
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return pNtkMapped;
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}
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Abc_Ntk_t *Gia_ManRewireMapNf(Gia_Man_t *pGia) {
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Jf_Par_t Pars, * pPars = &Pars;
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Nf_ManSetDefaultPars( pPars );
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Gia_Man_t *pGiaNew = Nf_ManPerformMapping(pGia, pPars);
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if (pGiaNew == NULL) {
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Abc_Print(-1, "Mapping has failed.\n");
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return NULL;
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}
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Abc_Ntk_t *pNtkMapped = Abc_NtkFromCellMappedGia(pGiaNew, 0);
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return pNtkMapped;
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}
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Abc_Ntk_t *Gia_ManRewireMapSimap(Gia_Man_t *pGia, int nBound, int nBTLimit, int nTimeout) {
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Abc_Print(-1, "[Warning] Gia_ManRewireMapSimap is SAT-based experimental mode.\n");
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if (!Gia_ManSimpleMapping(pGia, nBound, 0, nBTLimit, nTimeout, 0, 0, 0, NULL)) {
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// Abc_Print(-1, "Mapping has failed.\n");
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return NULL;
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}
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Abc_Ntk_t *pNtkMapped = Abc_NtkFromCellMappedGia(pGia, 0);
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return pNtkMapped;
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}
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Vec_Int_t *Abc_ManRewireNtkWriteMiniMapping(Abc_Ntk_t *pNtk) {
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return Abc_NtkWriteMiniMapping(pNtk);
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}
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Abc_Ntk_t *Abc_ManRewireNtkFromMiniMapping(int *vMapping) {
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return Abc_NtkFromMiniMapping(vMapping);
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}
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Mini_Aig_t *Abc_ManRewireMiniAigFromNtk(Abc_Ntk_t *pNtk) {
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return Abc_MiniAigFromNtk(pNtk);
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}
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ABC_NAMESPACE_IMPL_END |