mirror of https://github.com/YosysHQ/abc.git
21 lines
584 B
Plaintext
21 lines
584 B
Plaintext
- required time support
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- printing ABC version/platform in the output files
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- improve AIG rewriting package
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- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
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- SAT solver with linear constraints
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- specialized synthesis for EXORs and large MUXes
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- parser for Verilog netlists
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- required time based on all cuts
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- comparing tts of differently derived the same cut
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- area flow based AIG rewriting
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- cut frontier adjustment
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- box-aware dch, lcorr, and scorr with optional deboxing
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- mfs with boxes
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- power-aware mapping
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- full support of required times
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